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1. general description the p89lpc9151/9161/9171 is a single-chip microcontroller, available in low cost packages, based on a high performance processo r architecture that ex ecutes instructions in two to four clocks, six times the rate of standard 80c51 devices. many system-level functions have been incorporated into the device in order to reduce component count, board space, and system cost. 2. features 2.1 principal features ? 2 kb byte-erasable flash code memory organ ized into 256-byte sectors and 16-byte pages. single-byte erasing allows any byte(s) to be used as non-volatile data storage. ? 256-byte ram data memory. ? 4-input multiplexed 8-bit adc/single dac output. two analog comparators with selectable inputs and reference source. ? two 16-bit counter/timers. timer 0 (and timer 1 - p89lpc9171) may be configured to toggle a port output upon timer overflow or to become a pwm output. ? a 23-bit system timer that can also be used as real-time clock consisting of a 7-bit prescaler and a programmable and readable 16-bit timer. ? enhanced uart with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 khz byte-wide i 2 c-bus communication port. ? spi communication port (P89LPC9161). ? 2.4 v to 3.6 v v dd operating range. i/o pins are 5 v tolerant (may be pulled up or driven to 5.5 v). ? enhanced low voltage (brown out) detect allows a graceful system shutdown when power fails. ? 16-pin tssop with 12 i/o pins minimum and up to 14 i/o pins while using on-chip oscillator and reset options (P89LPC9161/9171), and 14-p in tssop packages with 10 i/o pins minimum and up to 12 i/o pins wh ile using on-chip oscilla tor and reset options (p89lpc9151). p89lpc9151/9161/9171 8-bit microcontroller with accel erated two-clock 80c51 core, 2 kb 3 v byte-erasable flash with 8-bit adc rev. 02 ? 9 february 2010 product data sheet
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 2 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 2.2 additional features ? a high performance 80c51 cpu provides instruction cycle times of 111 ns to 222 ns for all instructions exc ept multiply and divide when executing at 18 mhz. this is six times the performance of the standard 80c5 1 running at the same clock frequency. a lower clock frequency for the same performance results in power savings and reduced emi. ? in-application programming (iap-lite) and byte erase allows code memory to be used for non-volatile data storage. ? serial flash in-circuit programming (icp ) allows simple production coding with commercial eprom programmers. flash security bits prevent reading of sensitive application programs. ? watchdog timer with separate on -chip oscillator, nominal 400 khz, calibrated to 5 %, requiring no external components. the watchdog prescaler is selectable from eight values. ? high-accuracy intern al rc oscillator option, with clock doubler option, allows operation without external oscillator components. the rc oscillator option is selectable and fine tunable. ? clock switching on the fly amon g internal rc oscillator, wa tchdog oscillator, external clock input provides optimal support of mini mal power active mode with fast switching to maximum performance. ? idle and two different power-down reduced power modes. improved wake-up from power-down mode (a low interrupt input starts execution). typical power-down current is 1 a (total power-down with voltage comparators disabled). ? active-low reset. on-chip power-on reset allows operation without external reset components. a software reset function is also available. ? configurable on-chip oscilla tor with frequency range op tions selected by user programmed flash configurat ion bits. oscillator options support frequencies from 20 khz to the maximum operating frequency of 18 mhz. ? oscillator fail detect. the watchdog timer has a separate fully on-chip oscillator allowing it to perform an os cillator fail detect function. ? programmable port output configuration opti ons: quasi-bidirectional, open drain, push-pull, input-only. ? high current sourcing/sinking (20 ma) at 4 i/o pins on the p89lpc9151, 3 i/o pins on the P89LPC9161 and 5 i/o pins on the p89lpc9171. all other port pins have high sinking capability (20 ma). a maximum limit is specified for the entire chip. ? port ?input pattern match? detect. port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. ? controlled slew rate port outputs to reduce emi. outputs have approximately 10 ns minimum ramp times. ? only power and ground connections are required to operate the p89lpc9151/9161/9171 when internal reset option is selected. ? four interrupt pr iority levels. ? five/six keypad interrupt inputs, plus two additional external interrupt inputs. ? schmitt trigger port inputs. ? second data pointer. ? emulation support.
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 3 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 3. ordering information 3.1 ordering options table 1. ordering information type number package name description version p89lpc9151fdh tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 P89LPC9161fdh tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 p89lpc9171fdh tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 table 2. ordering options type number flash memory temperature range frequency p89lpc9151fdh 2 kb ? 40 c to +85 c 0 mhz to 18 mhz P89LPC9161fdh 2 kb ? 40 c to +85 c 0 mhz to 18 mhz p89lpc9171fdh 2 kb ? 40 c to +85 c 0 mhz to 18 mhz
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 4 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 4. block diagram fig 1. block diagram (p89lpc9151) 2 kb code flash i 2 c cmp2 cin2b cin2a cin1a cin1b cmpref p1[5:0] p0[5:0] txd rxd scl ad10 ad11 ad12 ad13 t0 p89lpc9151 002aae564 256 byte data ram port 1 configurable i/o port 0 configurable i/o keypad interrupt watchdog timer and oscillator programmable oscillator divider on-chip rc oscillator external clock input cpu clock internal bus high performance accelerated 2-clock 80c51 cpu uart adc1/dac1 real time clock/ system timer timer 0 timer 1 analog comparators power monitor (power-on reset, brownout reset) on-chip rc oscillator with clock doubler sda dac1
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 5 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc fig 2. block diagram (P89LPC9161) 2 kb code flash i 2 c cin2b cin2a cin1a cin1b cmpref p2[5:2] p1.5, p1[3:0] p0[5:1] txd rxd scl ad10 ad11 ad12 ad13 t0 spi mosi miso spiclk P89LPC9161 002aae565 ss 256 byte data ram port 2 configurable i/o port 1 configurable i/o port 0 configurable i/o keypad interrupt watchdog timer and oscillator programmable oscillator divider on-chip rc oscillator external clock input cpu clock internal bus high performance accelerated 2-clock 80c51 cpu uart adc1/dac1 real time clock/ system timer timer 0 timer 1 analog comparators power monitor (power-on reset, brownout reset) sda dac1 on-chip rc oscillator with clock doubler
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 6 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc fig 3. block diagram (p89lpc9171) 2 kb code flash i 2 c cmp2 cin2b cin2a cin1a cin1b cmpref p2.2 p1[5:0] p0.7, p[5:0] txd rxd scl ad10 ad11 ad12 ad13 t0 t1 p89lpc9171 002aae566 256 byte data ram port 2 configurable i/o port 1 configurable i/o port 0 configurable i/o keypad interrupt watchdog timer and oscillator programmable oscillator divider external clock input clkout cpu clock on-chip rc oscillator internal bus high performance accelerated 2-clock 80c51 cpu uart adc1/dac1 real time clock/ system timer timer 0 timer 1 analog comparators power monitor (power-on reset, brownout reset) sda dac1 on-chip rc oscillator with clock doubler
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 7 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 5. functional diagram fig 4. functional diagram (p89lpc9151) kbi0 kbi1 kbi2 kbi3 kbi4 kbi5 ad10 ad11 ad12 ad13 clkin cmp2 cin2b cin2a cin1b cin1a cmpref txd rxd t0 int0 int1 rst scl p89lpc9151 002aae567 v dd v ss dac1 port 0 port 1 sda fig 5. functional diagram (P89LPC9161) kbi1 kbi2 kbi3 kbi4 kbi5 ad10 ad11 ad12 ad13 clkin cin2b cin2a cin1b cin1a cmpref txd rxd t0 int0 mosi mis0 spiclk rst scl P89LPC9161 002aae568 v dd v ss ss dac1 port 0 port 1 port 2 sda
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 8 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc fig 6. functional diagram (p89lpc9171) kbi0 kbi1 kbi2 kbi3 kbi4 kbi5 ad10 ad11 ad12 ad13 clkin kbi7 cmp2 cin2b cin2a cin1b cin1a cmpref t1 txd rxd t0 int0 int1 rst scl p89lpc9171 002aae569 v dd v ss dac1 clkout port 0 port 1 port 2 sda
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 9 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 6. pinning information 6.1 pinning fig 7. p89lpc9151 tssop14 pin configuration fig 8. P89LPC9161 tssop16 pin configuration fig 9. p89lpc9171 tssop16 pin configuration p89lpc9151 p0.1/cin2b/kbi1/ad10 p0.2/cin2a/kbi2/ad11 p0.0/cmp2/kbi0 p0.3/cin1b/kbi3/ad12 p1.5/rst p0.4/cin1a/kbi4/ad13/dac1 v ss p0.5/cmpref/kbi5/clkin p1.4/int1 v dd p1.3/int0/sda p1.0/txd p1.2/t0/scl p1.1/rxd 002aae570 1 2 3 4 5 6 7 8 10 9 12 11 14 13 P89LPC9161 p0.1/cin2b/kbi1/ad10 p0.2/cin2a/kbi2/ad11 p2.4/ss p0.3/cin1b/kbi3/ad12 p1.5/rst p0.4/cin1a/kbi4/ad13/dac1 v ss p0.5/cmpref/kbi5/clkin p2.3/miso v dd p2.2/mosi p2.5/spiclk p1.3/int0/sda p1.0/txd p1.2/t0/scl p1.1/rxd 002aae571 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 p89lpc9171 p0.1/cin2b/kbi1/ad10 p0.2/cin2a/kbi2/ad11 p0.0/cmp2/kbi0 p0.3/cin1b/kbi3/ad12 p1.5/rst p0.4/cin1a/kbi4/ad13/dac1 v ss p0.5/cmpref/kbi5/clkin p2.2 v dd p1.4/int1 p0.7/t1/kbi7/clkout p1.3/int0/sda p1.0/txd p1.2/t0/scl p1.1/rxd 002aae572 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 10 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 6.2 pin description table 3. p89lpc9151 pin description symbol pin type description tssop14 p0.0 to p0.5 i/o port 0: port 0 is an 6-bit i/o port with a user-configurable output type. during reset port 0 latches are configured in the input only mode with the internal pull-up disabled. the operation of port 0 pins as inputs and outputs depends upon the port configuration selected. each port pi n is configured independently. refer to section 7.15.1 ? port configurations ? and table 16 ? static characteristics ? for details. the keypad interrupt feature operates with port 0 pins. all pins have schmitt trigger inputs. port 0 also provides various special functions as described below: p0.0/cmp2/ kbi0 2 i/o p0.0 ? port 0 bit 0. o cmp2 ? comparator 2 output i kbi0 ? keyboard input 0. p0.1/cin2b/ kbi1/ad10 1 i/o p0.1 ? port 0 bit 1. i cin2b ? comparator 2 positive input b. i kbi1 ? keyboard input 1. i ad10 ? adc1 channel 0 analog input. p0.2/cin2a/ kbi2/ad11 14 i/o p0.2 ? port 0 bit 2. i cin2a ? comparator 2 positive input a. i kbi2 ? keyboard input 2. i ad11 ? adc1 channel 1 analog input. p0.3/cin1b/ kbi3/ad12 13 i/o p0.3 ? port 0 bit 3. high current source. i cin1b ? comparator 1 positive input b. i kbi3 ? keyboard input 3. i ad12 ? adc1 channel 2 analog input. p0.4/cin1a/ kbi4/dac1/ad13 12 i/o p0.4 ? port 0 bit 4. high current source. i cin1a ? comparator 1 positive input a. i kbi4 ? keyboard input 4. o dac1 ? digital-to-analog converter output 1. i ad13 ? adc1 channel 3 analog input. p0.5/cmpref/ kbi5 11 i/o p0.5 ? port 0 bit 5. high current source. i cmpref ? comparator reference (negative) input. i kbi5 ? keyboard input 5. i clkin ? external clock input. p1.0 to p1.5 i/o, i [1] port 1: port 1 is an 6-bit i/o port with a user-configurable output type, except for three pins as noted below. during reset port 1 latches are configured in the input only mode with the internal pull-up disabl ed. the operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration selected. each of the configurable port pins ar e programmed independently. refer to section 7.15.1 ? port configurations ? and table 16 ? static characteristics ? for details. p1.2 to p1.3 are open drain when used as outputs. p1.5 is input only. all pins have schmitt trigger inputs. port 1 also provides various special functions as described below:
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 11 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc [1] input/output for p1.0 to p1.4. input for p1.5. p1.0/txd 9 i/o p1.0 ? port 1 bit 0. o txd ? transmitter output for serial port. p1.1/rxd 8 i/o p1.1 ? port 1 bit 1. i rxd ? receiver input for serial port. p1.2/t0/scl 7 i/o p1.2 ? port 1 bit 2 (open-drain when used as output). i/o t0 ? timer/counter 0 external count input or overflow output (open-drain when used as output). i/o scl ? i 2 c-bus serial clo ck input/output. p1.3/ int0 /sda 6 i/o p1.3 ? port 1 bit 3 (open-drain when used as output). i int0 ? external interrupt 0 input. i/o sda ? i 2 c-bus serial data input/output. p1.4/ int1 5 i/o p1.4 ? port 1 bit 4. high current source. i int1 ? external interrupt 1 input. p1.5/ rst 3 i p1.5 ? port 1 bit 5 (input only). i rst ? external reset input during power-on or if selected via ucfg1. when functioning as a reset input, a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor begins execution at address 0. also used during a power-on sequence to force isp mode. v ss 4 i ground: 0 v reference. v dd 10 i power supply: this is the power supply voltage for normal operation as well as idle and power-down modes. table 3. p89lpc9151 pin description symbol pin type description tssop14
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 12 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc table 4. P89LPC9161 pin description symbol pin type description tssop16 p0.1 to p0.5 i/o port 0: port 0 is an 5-bit i/o port with a user-configurable output type. during reset port 0 latches are configured in the input only mode with the internal pull-up disabled. the operation of port 0 pins as inputs and outputs depends upon the port configuration selected. each port pi n is configured independently. refer to section 7.15.1 ? port configurations ? and table 16 ? static characteristics ? for details. the keypad interrupt feature operates with port 0 pins. all pins have schmitt trigger inputs. port 0 also provides various special functions as described below: p0.1/cin2b/ kbi1/ad10 1 i/o p0.1 ? port 0 bit 1. i cin2b ? comparator 2 positive input b. i kbi1 ? keyboard input 1. i ad10 ? adc1 channel 0 analog input. p0.2/cin2a/ kbi2/ad11 16 i/o p0.2 ? port 0 bit 2. i cin2a ? comparator 2 positive input a. i kbi2 ? keyboard input 2. i ad11 ? adc1 channel 1 analog input. p0.3/cin1b/ kbi3/ad12 15 i/o p0.3 ? port 0 bit 3. high current source. i cin1b ? comparator 1 positive input b. i kbi3 ? keyboard input 3. i ad12 ? adc1 channel 2 analog input. p0.4/cin1a/ kbi4/dac1/ad13 14 i/o p0.4 ? port 0 bit 4. high current source. i cin1a ? comparator 1 positive input a. i kbi4 ? keyboard input 4. o dac1 ? digital-to-analog converter output 1. i ad13 ? adc1 channel 3 analog input. p0.5/cmpref/ kbi5 13 i/o p0.5 ? port 0 bit 5. high current source. i cmpref ? comparator reference (negative) input. i kbi5 ? keyboard input 5. i clkin ? external clock input. p1.0 to p1.3, p1.5 i/o, i [1] port 1: port 1 is an 5-bit i/o port with a user-configurable output type, except for three pins as noted below. during reset port 1 latches are configured in the input only mode with the internal pull-up disabl ed. the operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration selected. each of the configurable port pins ar e programmed independently. refer to section 7.15.1 ? port configurations ? and table 16 ? static characteristics ? for details. p1.2 to p1.3 are open drain when used as outputs. p1.5 is input only. all pins have schmitt trigger inputs. port 1 also provides various special functions as described below: p1.0/txd 10 i/o p1.0 ? port 1 bit 0. o txd ? transmitter output for serial port. p1.1/rxd 9 i/o p1.1 ? port 1 bit 1. i rxd ? receiver input for serial port.
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 13 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc [1] input/output for p1.0 to p1.3. input for p1.5. p1.2/t0/scl 8 i/o p1.2 ? port 1 bit 2 (open-drain when used as output). i/o t0 ? timer/counter 0 external count input or overflow output (open-drain when used as output). i/o scl ? i 2 c-bus serial clo ck input/output. p1.3/ int0 /sda 7 i/o p1.3 ? port 1 bit 3 (open-drain when used as output). i int0 ? external interrupt 0 input. i/o sda ? i 2 c-bus serial data input/output. p1.5/ rst 3 i p1.5 ? port 1 bit 5 (input only). i rst ? external reset input during power-on or if selected via ucfg1. when functioning as a reset input, a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor begins execution at address 0. also used during a power-on sequence to force isp mode. p2.2 to p2.5 i/o port 2: port 2 is an 4-bit i/o port with a user-configurable output type. during reset port 2 latches are configured in the input only mode with the internal pull-up disabled. the operation of port 2 pins as inputs and outputs depends upon the port configuration selected. each port pi n is configured independently. refer to section 7.15 ? i/o ports ? for details. all pins have schmitt trigger inputs. port 2 also provides various special functions as described below: p2.2/mosi 6 i/o p2.2 ? port 2 bit 2. i/o mosi ? spi master out slave in. when config ured as master, this pin is output; when configured as slave, this pin is input. p2.3/miso 5 i/o p2.3 ? port 2 bit 3. i/o miso ? when configured as master, this pi n is input, when configured as slave, this pin is output. p2.4/ ss 2 i/o p2.4 ? port 2 bit 4. i ss ? spi slave select. p2.5/spiclk 11 i/o p2.5 ? port 2 bit 5. i/o spiclk ? spi clock. when configured as master, this pin is output; when configured as slave, this pin is input. v ss 4 i ground: 0 v reference. v dd 12 i power supply: this is the power supply voltage for normal operation as well as idle and power-down modes. table 4. P89LPC9161 pin description symbol pin type description tssop16
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 14 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc table 5. p89lpc9171 pin description symbol pin type description tssop16 p0.0 to p0.5, p0.7 i/o port 0: port 0 is an 6-bit i/o port with a user-configurable output type. during reset port 0 latches are configured in the input only mode with the internal pull-up disabled. the operation of port 0 pins as inputs and outputs depends upon the port configuration selected. each port pi n is configured independently. refer to section 7.15.1 ? port configurations ? and table 16 ? static characteristics ? for details. the keypad interrupt feature operates with port 0 pins. all pins have schmitt trigger inputs. port 0 also provides various special functions as described below: p0.0/cmp2/ kbi0 2 i/o p0.0 ? port 0 bit 0. o cmp2 ? comparator 2 output i kbi0 ? keyboard input 0. p0.1/cin2b/ kbi1/ad10 1 i/o p0.1 ? port 0 bit 1. i cin2b ? comparator 2 positive input b. i kbi1 ? keyboard input 1. i ad10 ? adc1 channel 0 analog input. p0.2/cin2a/ kbi2/ad11 16 i/o p0.2 ? port 0 bit 2. i cin2a ? comparator 2 positive input a. i kbi2 ? keyboard input 2. i ad11 ? adc1 channel 1 analog input. p0.3/cin1b/ kbi3/ad12 15 i/o p0.3 ? port 0 bit 3. high current source. i cin1b ? comparator 1 positive input b. i kbi3 ? keyboard input 3. i ad12 ? adc1 channel 2 analog input. p0.4/cin1a/ kbi4/dac1/ad13 14 i/o p0.4 ? port 0 bit 4. high current source. i cin1a ? comparator 1 positive input a. i kbi4 ? keyboard input 4. o dac1 ? digital-to-analog converter output 1. i ad13 ? adc1 channel 3 analog input. p0.5/cmpref/ kbi5/clkin 13 i/o p0.5 ? port 0 bit 5. high current source. i cmpref ? comparator reference (negative) input. i kbi5 ? keyboard input 5. i clkin ? external clock input. p0.7/t1/ kbi7/clk out 11 i/o p0.7 ? port 0 bit 7. high current source. i/o t1 ? timer/counter 1 external count input or overflow output. i kbi7 ? keyboard input 7. o clkout ? clock output.
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 15 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc [1] input/output for p1.0 to p1.4. input for p1.5. p1.0 to p1.5 i/o, i [1] port 1: port 1 is an 6-bit i/o port with a user-configurable output type, except for three pins as noted below. during reset port 1 latches are configured in the input only mode with the internal pull-up disabl ed. the operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration selected. each of the configurable port pins ar e programmed independently. refer to section 7.15.1 ? port configurations ? and table 16 ? static characteristics ? for details. p1.2 to p1.3 are open drain when used as outputs. p1.5 is input only. all pins have schmitt trigger inputs. port 1 also provides various special functions as described below: p1.0/txd 10 i/o p1.0 ? port 1 bit 0. o txd ? transmitter output for serial port. p1.1/rxd 9 i/o p1.1 ? port 1 bit 1. i rxd ? receiver input for serial port. p1.2/t0/scl 8 i/o p1.2 ? port 1 bit 2 (open-drain when used as output). i/o t0 ? timer/counter 0 external count input or overflow output (open-drain when used as output). i/o scl ? i 2 c-bus serial clo ck input/output. p1.3/ int0 /sda 7 i/o p1.3 ? port 1 bit 3 (open-drain when used as output). i int0 ? external interrupt 0 input. i/o sda ? i 2 c-bus serial data input/output. p1.4/ int1 6 i/o p1.4 ? port 1 bit 4. high current source. i int1 ? external interrupt 1 input. p1.5/ rst 3 i p1.5 ? port 1 bit 5 (input only). i rst ? external reset input during power-on or if selected via ucfg1. when functioning as a reset input, a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor begins execution at address 0. also used during a power-on sequence to force isp mode. p2.2 5 i/o port 2: p2.2 is a single-bit i/o port with a user-configurable output type. during reset p2.2 latch is configured in the input only mode with the internal pull-up disabled. the operation of the output depends upon the po rt configuration selected. refer to section 7.15 ? i/o ports ? for details. this pin has schmitt trigger inputs. v ss 4 i ground: 0 v reference. v dd 12 i power supply: this is the power supply voltage for normal operation as well as idle and power-down modes. table 5. p89lpc9171 pin description symbol pin type description tssop16
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 16 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 7. functional description remark: please refer to the p89lpc9151/9161/9171 user manual for a more detailed functional description. 7.1 special function registers remark: sfr accesses are restricted in the following ways: ? user must not attempt to access any sfr locations not defined. ? accesses to any defined sfr locations must be strictly for the functions for the sfrs. ? sfr bits labeled ?-?, ?0? or ?1? can only be written and read as follows: ? ?-? unless otherwise specified, must be written with ?0?, but can return any value when read (even if it was wr itten with ?0?). it is a reserved bit and may be used in future derivatives. ? ?0? must be written with ?0?, and will return a ?0? when read. ? ?1? must be written with ?1?, and will return a ?1? when read.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 17 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc table 6. special function registers - p89lpc9151 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary bit address e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h 00 0000 0000 adcon1 a/d control register 1 97h enbi1 enadci1 tmm1 edge1 adci1 enadc1 adcs11 adcs10 00 0000 0000 adins a/d input select a3h ain13 ain12 ain11 ain10 - - - - 00 0000 0000 admoda a/d mode register a c0h bndi1 burst1 scc1 scan1 - - - - 00 0000 0000 admodb a/d mode register b a1h clk2 clk1 clk0 inbnd0 endac1 - bsa1 - 00 000x 0000 ad1bh a/d_0 boundary high register c4h ff 1111 1111 ad1bl a/d_0 boundary low register bch 00 0000 0000 ad1dat0 a/d_0 data register 0 d5h 00 0000 0000 ad1dat1 a/d_0 data register 1 d6h 00 0000 0000 ad1dat2 a/d_0 data register 2 d7h 00 0000 0000 ad1dat3 a/d_0 data register 3 f5h 00 0000 0000 auxr1 auxiliary function register a2h clklp ebrr - ent0 srst 0 - dps 00 0000 00x0 bit address f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h 00 0000 0000 brgr0 [2] baud rate generator 0 rate low beh 00 0000 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 18 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc brgr1 [2] baud rate generator 0 rate high bfh 00 0000 0000 brgcon baud rate generator 0 control bdh - - - - - - sbrgs brgen 00 [2] xxxx xx00 cmp1 comparator 1 control register ach - - ce1 cp1 cn1 - co1 cmf1 00 [1] xx00 0000 cmp2 comparator 2 control register adh - - ce2 cp2 cn2 oe2 co2 cmf2 00 [1] xx00 0000 divm cpu clock divide-by-m control 95h 00 0000 0000 dptr data pointer (2 bytes) dph data pointer high 83h 00 0000 0000 dpl data pointer low 82h 00 0000 0000 fmadrh program flash address high e7h 00 0000 0000 fmadrl program flash address low e6h 00 0000 0000 fmcon program flash control (read) e4h busy - - - hva hve sv oi 70 0111 0000 program flash control (write) e4h fmcmd.7 fmcmd.6 fmcmd.5 fmcmd.4 fmcmd.3 fmcmd.2 fmcmd.1 fmcmd.0 fmdata program flash data e5h 00 0000 0000 i2adr i 2 c-bus slave address register dbh i2adr.6 i2adr.5 i2adr.4 i2adr.3 i2adr.2 i2adr.1 i2adr.0 gc 00 0000 0000 table 6. special function registers - p89lpc9151 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 19 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc bit address df de dd dc db da d9 d8 i2con* i 2 c-bus control register d8h - i2en sta sto si aa - crsel 00 x000 00x0 i2dat i 2 c-bus data register dah i2sclh serial clock generator/scl duty cycle register high ddh 00 0000 0000 i2scll serial clock generator/scl duty cycle register low dch 00 0000 0000 i2stat i 2 c-bus status register d9h sta.4 sta.3 sta.2 sta.1 sta.0 0 0 0 f8 1111 1000 bit address af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ewdrt ebo es/esr et1 ex1 et0 ex0 00 0000 0000 bit address ef ee ed ec eb ea e9 e8 ien1* interrupt enable 1 e8h ead est - - - ec ekbi ei2c 00 [1] 00x0 0000 bit address bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h - pwdrt pbo ps/psr pt1 px1 pt0 px0 00 [1] x000 0000 ip0h interrupt priority 0 high b7h - pwdrth pboh psh/ psrh pt1h px1h pt0h px0h 00 [1] x000 0000 bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h pad pst - - - pc pkbi pi2c 00 [1] 00x0 0000 ip1h interrupt priority 1 high f7h padh psth - - - pch pkbih pi2ch 00 [1] 00x0 0000 kbcon keypad control register 94h - - - - - - patn _sel kbif 00 [1] xxxx xx00 table 6. special function registers - p89lpc9151 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 20 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc kbmask keypad interrupt mask register 86h 00 0000 0000 kbpatn keypad pattern register 93h ff 1111 1111 bit address 87 86 85 84 83 82 81 80 p0* port 0 80h - - cmpref /kb5 /clkin cin1a /kb4 cin1b /kb3 cin2a /kb2 cin2b /kb1 cmp2 /kb0 [1] bit address 97 96 95 94 93 92 91 90 p1* port 1 90h - - rst int1 int0 /sda t0/scl rxd txd [1] bit address b7 b6 b5 b4 b3 b2 b1 b0 p0m1 port 0 output mode 1 84h - - (p0m1.5) (p0m1.4) (p0m1.3) (p0m1.2) (p0m1.1) (p0m1.0) ff [1] 1111 1111 p0m2 port 0 output mode 2 85h - - (p0m2.5) (p0m2.4) (p0m2.3) (p0m2.2) (p0m2.1) (p0m2.0) 00 [1] 0000 0000 p1m1 port 1 output mode 1 91h - - - (p1m1.4) (p1m1.3) (p1m1.2) (p1m1.1) (p1m1.0) d3 [1] 11x1 xx11 p1m2 port 1 output mode 2 92h - - - (p1m2.4) (p1m2.3) (p1m2.2) (p1m2.1) (p1m2.0) 00 [1] 00x0 xx00 pcon power control register 87h smod1 smod0 - boi gf1 gf0 pmod1 pmod0 00 0000 0000 pcona power control register a b5h rtcpd - vcpd adpd i2pd - spd - 00 [1] 0000 0000 bit address d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00 0000 0000 pt0ad port 0 digital input disable f6h - - pt0ad.5 pt0ad.4 pt0ad.3 pt0ad.2 pt0ad.1 - 00 xx00 000x rstsrc reset source register dfh - boif bof pof r_bk r_wd r_sf r_ex [3] rtccon rtc control d1h rtcf rtcs1 rtcs0 - - - ertc rtcen 60 [1] [6] 011x xx00 table 6. special function registers - p89lpc9151 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 21 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc rtch rtc register high d2h 00 [6] 0000 0000 rtcl rtc register low d3h 00 [6] 0000 0000 saddr serial port address register a9h 00 0000 0000 saden serial port address enable b9h 00 0000 0000 sbuf serial port data buffer register 99h xx xxxx xxxx bit address 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00 0000 0000 sstat serial port extended status register bah dbmod intlo cidis dbisel fe br oe stint 00 0000 0000 sp stack pointer 81h 07 0000 0111 tamod timer 0 and 1 auxiliary mode 8fh - - - - - - - t0m2 00 xxx0 xxx0 bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer 0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 0000 0000 th0 timer 0 high 8ch 00 0000 0000 th1 timer 1 high 8dh 00 0000 0000 tl0 timer 0 low 8ah 00 0000 0000 tl1 timer 1 low 8bh 00 0000 0000 tmod timer 0 and 1 mode 89h t1gate t1c/ t t1m1 t1m0 t0gate t0c/ t t0m1 t0m0 00 0000 0000 trim internal oscillator trim register 96h rcclk - trim.5 trim.4 trim.3 trim.2 trim.1 trim.0 [5] [6] table 6. special function registers - p89lpc9151 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 22 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc [1] all ports are in input only (high-impedance) state after power-up. [2] brgr1 and brgr0 must only be written if brgen in brgcon sfr is logic 0. if any are written while brgen = 1, the result is unpredictable. [3] the rstsrc register reflects the cause of the p89lpc9151 rese t except boif bit. upon a power-up reset, all reset source flag s are cleared except pof and bof; the power-on reset value is x011 0000. [4] after reset, the value is 1110 01x1, i.e., pre2 to pre0 are all logic 1, wdrun = 1 and wdclk = 1. wdtof bit is logic 1 after watchdog reset and is logic 0 after power-on reset. other resets will not affect wdtof. [5] on power-on reset and watchdog reset, the trim sfr is initialized with a factory preprogrammed value. other resets will not cause initialization of the trim register. [6] the only reset sources that affect these sfrs are power-on reset and watchdog reset. wdcon watchdog control register a7h pre2 pre1 pre0 - - wdrun wdtof wdclk [4] [6] wdl watchdog load c1h ff 1111 1111 wfeed1 watchdog feed 1 c2h wfeed2 watchdog feed 2 c3h table 6. special function registers - p89lpc9151 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 23 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc [1] extended sfrs are physically located on-chip but logically loca ted in external data memory address space (xdata). the movx a ,@dptr and movx @dptr,a instructions are used to access these extended sfrs. [2] the boicfg1/0 will be copied from ucfg1.5 and ucfg1.3 when power-on reset. [3] clkcon register reset value comes from ucfg1 and ucfg2. the rese t value of clkcon.2 to clkcon.0 come from ucfg1.2 to ucfg1.0 and reset value of clkdbl bit comes from ucfg2.7. table 7. extended special function registers - p89lpc9151 [1] name description sfr addr. bit functions and addresses reset value msb lsb hex binary bodcfg bod configuration register ffc8h - - - - - - boicfg1 boicfg0 [2] clkcon clock control register ffdeh clkok - - - clkdbl fosc2 fosc1 fosc0 [3] rtcdath real-time clock data register high ffbfh 00 0000 0000 rtcdatl real-time clock data register low ffbeh 00 0000 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 24 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc table 8. special function registers - P89LPC9161 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary bit address e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h 00 0000 0000 adcon1 a/d control register 1 97h enbi1 enadci1 tmm1 edge1 adci1 enadc1 adcs11 adcs10 00 0000 0000 adins a/d input select a3h ain13 ain12 ain11 ain10 - - - - 00 0000 0000 admoda a/d mode register a c0h bndi1 burst1 scc1 scan1 - - - - 00 0000 0000 admodb a/d mode register b a1h clk2 clk1 clk0 inbnd0 endac1 - bsa1 - 00 000x 0000 ad1bh a/d_0 boundary high register c4h ff 1111 1111 ad1bl a/d_0 boundary low register bch 00 0000 0000 ad1dat0 a/d_0 data register 0 d5h 00 0000 0000 ad1dat1 a/d_0 data register 1 d6h 00 0000 0000 ad1dat2 a/d_0 data register 2 d7h 00 0000 0000 ad1dat3 a/d_0 data register 3 f5h 00 0000 0000 auxr1 auxiliary function register a2h clklp ebrr - ent0 srst 0 - dps 00 0000 00x0 bit address f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h 00 0000 0000 brgr0 [2] baud rate generator 0 rate low beh 00 0000 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 25 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc brgr1 [2] baud rate generator 0 rate high bfh 00 0000 0000 brgcon baud rate generator 0 control bdh - - - - - - sbrgs brgen 00 [2] xxxx xx00 cmp1 comparator 1 control register ach - - ce1 cp1 cn1 - co1 cmf1 00 [1] xx00 0000 cmp2 comparator 2 control register adh - - ce2 cp2 cn2 - co2 cmf2 00 [1] xx00 0000 divm cpu clock divide-by-m control 95h 00 0000 0000 dptr data pointer (2 bytes) dph data pointer high 83h 00 0000 0000 dpl data pointer low 82h 00 0000 0000 fmadrh program flash address high e7h 00 0000 0000 fmadrl program flash address low e6h 00 0000 0000 fmcon program flash control (read) e4h busy - - - hva hve sv oi 70 0111 0000 program flash control (write) e4h fmcmd.7 fmcmd.6 fmcmd.5 fmcmd.4 fmcmd.3 fmcmd.2 fmcmd.1 fmcmd.0 fmdata program flash data e5h 00 0000 0000 i2adr i 2 c-bus slave address register dbh i2adr.6 i2adr.5 i2adr.4 i2adr.3 i2adr.2 i2adr.1 i2adr.0 gc 00 0000 0000 table 8. special function registers - P89LPC9161 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 26 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc bit address df de dd dc db da d9 d8 i2con* i 2 c-bus control register d8h - i2en sta sto si aa - crsel 00 x000 00x0 i2dat i 2 c-bus data register dah i2sclh serial clock generator/scl duty cycle register high ddh 00 0000 0000 i2scll serial clock generator/scl duty cycle register low dch 00 0000 0000 i2stat i 2 c-bus status register d9h sta.4 sta.3 sta.2 sta.1 sta.0 0 0 0 f8 1111 1000 bit address af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ewdrt ebo es/esr et1 - et0 ex0 00 0000 0000 bit address ef ee ed ec eb ea e9 e8 ien1* interrupt enable 1 e8h ead est - - espi ec ekbi ei2c 00 [1] 00x0 0000 bit address bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h - pwdrt pbo ps/psr pt1 - pt0 px0 00 [1] x000 0000 ip0h interrupt priority 0 high b7h - pwdrth pboh psh/ psrh pt1h - pt0h px0h 00 [1] x000 0000 bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h pad pst - - pspi pc pkbi pi2c 00 [1] 00x0 0000 ip1h interrupt priority 1 high f7h padh psth - - pspih pch pkbih pi2ch 00 [1] 00x0 0000 kbcon keypad control register 94h - - - - - - patn _sel kbif 00 [1] xxxx xx00 table 8. special function registers - P89LPC9161 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 27 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc kbmask keypad interrupt mask register 86h 00 0000 0000 kbpatn keypad pattern register 93h ff 1111 1111 bit address 87 86 85 84 83 82 81 80 p0* port 0 80h - - cmpref /kb5 /clkin cin1a /kb4 cin1b /kb3 cin2a /kb2 cin2b /kb1 - [1] bit address 97 96 95 94 93 92 91 90 p1* port 1 90h - - rst - int0 /sda t0/scl rxd txd [1] bit address a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h - - spiclk ss miso mosi - - [1] p0m1 port 0 output mode 1 84h - - (p0m1.5) (p0m1.4) (p0m1.3) (p0m1.2) (p0m1.1) - ff [1] 1111 1111 p0m2 port 0 output mode 2 85h - - (p0m2.5) (p0m2.4) (p0m2.3) (p0m2.2) (p0m2.1) - 00 [1] 0000 0000 p1m1 port 1 output mode 1 91h - - - - (p1m1.3) (p1m1.2) (p1m1.1) (p1m1.0) d3 [1] 11x1 xx11 p1m2 port 1 output mode 2 92h - - - - (p1m2.3) (p1m2.2) (p1m2.1) (p1m2.0) 00 [1] 00x0 xx00 p2m1 port 2 output mode 1 a4h - - (p2m1.5) (p2m1.4) (p2m1.3) (p2m1.2) - - 03 [1] xxxx xx11 p2m2 port 2 output mode 2 a5h - - (p2m2.5) (p2m2.4) (p2m2.3) (p2m2.2) - - 00 [1] xxxx xx00 pcon power control register 87h smod1 smod0 - boi gf1 gf0 pmod1 pmod0 00 0000 0000 pcona power control register a b5h rtcpd - vcpd adpd i2pd sppd spd - 00 [1] 0000 0000 bit address d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00 0000 0000 table 8. special function registers - P89LPC9161 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 28 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc pt0ad port 0 digital input disable f6h - - pt0ad.5 pt0ad.4 pt0ad.3 pt0ad.2 pt0ad.1 - 00 xx00 000x rstsrc reset source register dfh - boif bof pof r_bk r_wd r_sf r_ex [3] rtccon rtc control d1h rtcf rtcs1 rtcs0 - - - ertc rtcen 60 [1] [6] 011x xx00 rtch rtc register high d2h 00 [6] 0000 0000 rtcl rtc register low d3h 00 [6] 0000 0000 saddr serial port address register a9h 00 0000 0000 saden serial port address enable b9h 00 0000 0000 sbuf serial port data buffer register 99h xx xxxx xxxx bit address 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00 0000 0000 sstat serial port extended status register bah dbmod intlo cidis dbisel fe br oe stint 00 0000 0000 sp stack pointer 81h 07 0000 0111 spctl spi control register e2h ssig spen dord mstr cpol cpha spr1 spr0 04 0000 0100 spstat spi status register e1h spif wcol - - - - - - 00 00xx xxxx spdat spi data register e3h 00 0000 0000 tamod timer 0 and 1 auxiliary mode 8fh - - - - - - - t0m2 00 xxx0 xxx0 table 8. special function registers - P89LPC9161 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 29 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc [1] all ports are in input only (high-impedance) state after power-up. [2] brgr1 and brgr0 must only be written if brgen in brgcon sfr is logic 0. if any are written while brgen = 1, the result is unpredictable. [3] the rstsrc register reflects the cause of the P89LPC9161 rese t except boif bit. upon a power-up reset, all reset source flag s are cleared except pof and bof; the power-on reset value is x011 0000. [4] after reset, the value is 1110 01x1, i.e., pre2 to pre0 are all logic 1, wdrun = 1 and wdclk = 1. wdtof bit is logic 1 after watchdog reset and is logic 0 after power-on reset. other resets will not affect wdtof. [5] on power-on reset and watchdog reset, the trim sfr is initialized with a factory preprogrammed value. other resets will not cause initialization of the trim register. [6] the only reset sources that affect these sfrs are power-on reset and watchdog reset. bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer 0 and 1 control 88h tf1 tr1 tf0 tr0 - - ie0 it0 00 0000 0000 th0 timer 0 high 8ch 00 0000 0000 th1 timer 1 high 8dh 00 0000 0000 tl0 timer 0 low 8ah 00 0000 0000 tl1 timer 1 low 8bh 00 0000 0000 tmod timer 0 and 1 mode 89h t1gate t1c/ t t1m1 t1m0 t0gate t0c/ t t0m1 t0m0 00 0000 0000 trim internal oscillator trim register 96h rcclk - trim.5 trim.4 trim.3 trim.2 trim.1 trim.0 [5] [6] wdcon watchdog control register a7h pre2 pre1 pre0 - - wdrun wdtof wdclk [4] [6] wdl watchdog load c1h ff 1111 1111 wfeed1 watchdog feed 1 c2h wfeed2 watchdog feed 2 c3h table 8. special function registers - P89LPC9161 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 30 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc [1] extended sfrs are physically located on-chip but logically loca ted in external data memory address space (xdata). the movx a ,@dptr and movx @dptr,a instructions are used to access these extended sfrs. [2] the boicfg1/0 will be copied from ucfg1.5 and ucfg1.3 when power-on reset. [3] clkcon register reset value comes from ucfg1 and ucfg2. the rese t value of clkcon.2 to clkcon.0 come from ucfg1.2 to ucfg1.0 and reset value of clkdbl bit comes from ucfg2.7. table 9. extended special function registers - P89LPC9161 [1] name description sfr addr. bit functions and addresses reset value msb lsb hex binary bodcfg bod configuration register ffc8h - - - - - - boicfg1 boicfg0 [2] clkcon clock control register ffdeh clkok - - - clkdbl fosc2 fosc1 fosc0 [3] rtcdath real-time clock data register high ffbfh 00 0000 0000 rtcdatl real-time clock data register low ffbeh 00 0000 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 31 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc table 10. special function registers - p89lpc9171 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary bit address e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h 00 0000 0000 adcon1 a/d control register 1 97h enbi1 enadci1 tmm1 edge1 adci1 enadc1 adcs11 adcs10 00 0000 0000 adins a/d input select a3h ain13 ain12 ain11 ain10 - - - - 00 0000 0000 admoda a/d mode register a c0h bndi1 burst1 scc1 scan1 - - - - 00 0000 0000 admodb a/d mode register b a1h clk2 clk1 clk0 inbnd0 endac1 - bsa1 - 00 000x 0000 ad1bh a/d_0 boundary high register c4h ff 1111 1111 ad1bl a/d_0 boundary low register bch 00 0000 0000 ad1dat0 a/d_0 data register 0 d5h 00 0000 0000 ad1dat1 a/d_0 data register 1 d6h 00 0000 0000 ad1dat2 a/d_0 data register 2 d7h 00 0000 0000 ad1dat3 a/d_0 data register 3 f5h 00 0000 0000 auxr1 auxiliary function register a2h clklp ebrr ent1 ent0 srst 0 - dps 00 0000 00x0 bit address f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h 00 0000 0000 brgr0 [2] baud rate generator 0 rate low beh 00 0000 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 32 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc brgr1 [2] baud rate generator 0 rate high bfh 00 0000 0000 brgcon baud rate generator 0 control bdh - - - - - - sbrgs brgen 00 [2] xxxx xx00 cmp1 comparator 1 control register ach - - ce1 cp1 cn1 - co1 cmf1 00 [1] xx00 0000 cmp2 comparator 2 control register adh - - ce2 cp2 cn2 oe2 co2 cmf2 00 [1] xx00 0000 divm cpu clock divide-by-m control 95h 00 0000 0000 dptr data pointer (2 bytes) dph data pointer high 83h 00 0000 0000 dpl data pointer low 82h 00 0000 0000 fmadrh program flash address high e7h 00 0000 0000 fmadrl program flash address low e6h 00 0000 0000 fmcon program flash control (read) e4h busy - - - hva hve sv oi 70 0111 0000 program flash control (write) e4h fmcmd.7 fmcmd.6 fmcmd.5 fmcmd.4 fmcmd.3 fmcmd.2 fmcmd.1 fmcmd.0 fmdata program flash data e5h 00 0000 0000 i2adr i 2 c-bus slave address register dbh i2adr.6 i2adr.5 i2adr.4 i2adr.3 i2adr.2 i2adr.1 i2adr.0 gc 00 0000 0000 table 10. special function registers - p89lpc9171 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 33 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc bit address df de dd dc db da d9 d8 i2con* i 2 c-bus control register d8h - i2en sta sto si aa - crsel 00 x000 00x0 i2dat i 2 c-bus data register dah i2sclh serial clock generator/scl duty cycle register high ddh 00 0000 0000 i2scll serial clock generator/scl duty cycle register low dch 00 0000 0000 i2stat i 2 c-bus status register d9h sta.4 sta.3 sta.2 sta.1 sta.0 0 0 0 f8 1111 1000 bit address af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ewdrt ebo es/esr et1 ex1 et0 ex0 00 0000 0000 bit address ef ee ed ec eb ea e9 e8 ien1* interrupt enable 1 e8h ead est - - - ec ekbi ei2c 00 [1] 00x0 0000 bit address bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h - pwdrt pbo ps/psr pt1 px1 pt0 px0 00 [1] x000 0000 ip0h interrupt priority 0 high b7h - pwdrth pboh psh/ psrh pt1h px1h pt0h px0h 00 [1] x000 0000 bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h pad pst - - - pc pkbi pi2c 00 [1] 00x0 0000 ip1h interrupt priority 1 high f7h padh psth - - - pch pkbih pi2ch 00 [1] 00x0 0000 kbcon keypad control register 94h - - - - - - patn _sel kbif 00 [1] xxxx xx00 table 10. special function registers - p89lpc9171 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 34 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc kbmask keypad interrupt mask register 86h 00 0000 0000 kbpatn keypad pattern register 93h ff 1111 1111 bit address 87 86 85 84 83 82 81 80 p0* port 0 80h t1/kb7 /clkout - cmpref /kb5 /clkin cin1a /kb4 cin1b /kb3 cin2a /kb2 cin2b /kb1 cmp2 /kbi0 00 [1] bit address 97 96 95 94 93 92 91 90 p1* port 1 90h - - rst int1 int0 /sda t0/scl rxd txd [1] bit address a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h - - - - - - - - [1] p0m1 port 0 output mode 1 84h (p0m1.7) - (p0m1.5) (p0m1.4) (p0m1.3) (p0m1.2) (p0m1.1) (p0m1.0) ff [1] 1111 1111 p0m2 port 0 output mode 2 85h (p0m2.7) - (p0m2.5) (p0m2.4) (p0m2.3) (p0m2.2) (p0m2.1) (p0m2.0) 00 [1] 0000 0000 p1m1 port 1 output mode 1 91h - - - - (p1m1.3) (p1m1.2) (p1m1.1) (p1m1.0) d3 [1] 11x1 xx11 p1m2 port 1 output mode 2 92h - - - - (p1m2.3) (p1m2.2) (p1m2.1) (p1m2.0) 00 [1] 00x0 xx00 p2m1 port 2 output mode 1 a4h - - - - - (p2m1.2) - - ff [1] 1111 1111 p2m2 port 2 output mode 2 a5h - - - - - (p2m2.2) - - 00 [1] 0000 0000 pcon power control register 87h smod1 smod0 - boi gf1 gf0 pmod1 pmod0 00 0000 0000 pcona power control register a b5h rtcpd - vcpd adpd i2pd - spd - 00 [1] 0000 0000 bit address d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00 0000 0000 table 10. special function registers - p89lpc9171 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 35 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc pt0ad port 0 digital input disable f6h - - pt0ad.5 pt0ad.4 pt0ad.3 pt0ad.2 pt0ad.1 - 00 xx00 000x rstsrc reset source register dfh - boif bof pof r_bk r_wd r_sf r_ex [3] rtccon rtc control d1h rtcf rtcs1 rtcs0 - - - ertc rtcen 60 [1] [6] 011x xx00 rtch rtc register high d2h 00 [6] 0000 0000 rtcl rtc register low d3h 00 [6] 0000 0000 saddr serial port address register a9h 00 0000 0000 saden serial port address enable b9h 00 0000 0000 sbuf serial port data buffer register 99h xx xxxx xxxx bit address 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00 0000 0000 sstat serial port extended status register bah dbmod intlo cidis dbisel fe br oe stint 00 0000 0000 sp stack pointer 81h 07 0000 0111 tamod timer 0 and 1 auxiliary mode 8fh - - - t1m2 - - - t0m2 00 xxx0 xxx0 bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer 0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 0000 0000 th0 timer 0 high 8ch 00 0000 0000 th1 timer 1 high 8dh 00 0000 0000 tl0 timer 0 low 8ah 00 0000 0000 tl1 timer 1 low 8bh 00 0000 0000 table 10. special function registers - p89lpc9171 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 36 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc [1] all ports are in input only (high-impedance) state after power-up. [2] brgr1 and brgr0 must only be written if brgen in brgcon sfr is logic 0. if any are written while brgen = 1, the result is unpredictable. [3] the rstsrc register reflects the cause of the p89lpc9171 rese t except boif bit. upon a power-up reset, all reset source flag s are cleared except pof and bof; the power-on reset value is x011 0000. [4] after reset, the value is 1110 01x1, i.e., pre2 to pre0 are all logic 1, wdrun = 1 and wdclk = 1. wdtof bit is logic 1 after watchdog reset and is logic 0 after power-on reset. other resets will not affect wdtof. [5] on power-on reset and watchdog reset, the trim sfr is initialized with a factory preprogrammed value. other resets will not cause initialization of the trim register. [6] the only reset sources that affect these sfrs are power-on reset and watchdog reset. tmod timer 0 and 1 mode 89h t1gate t1c/ t t1m1 t1m0 t0gate t0c/ t t0m1 t0m0 00 0000 0000 trim internal oscillator trim register 96h rcclk enclk trim.5 trim.4 trim.3 trim.2 trim.1 trim.0 [5] [6] wdcon watchdog control register a7h pre2 pre1 pre0 - - wdrun wdtof wdclk [4] [6] wdl watchdog load c1h ff 1111 1111 wfeed1 watchdog feed 1 c2h wfeed2 watchdog feed 2 c3h table 10. special function registers - p89lpc9171 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 37 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc [1] extended sfrs are physically located on-chip but logically loca ted in external data memory address space (xdata). the movx a ,@dptr and movx @dptr,a instructions are used to access these extended sfrs. [2] the boicfg1/0 will be copied from ucfg1.5 and ucfg1.3 when power-on reset. [3] clkcon register reset value comes from ucfg1 and ucfg2. the rese t value of clkcon.2 to clkcon.0 come from ucfg1.2 to ucfg1.0 and reset value of clkdbl bit comes from ucfg2.7. table 11. extended special func tion registers - p89lpc9171 [1] name description sfr addr. bit functions and addresses reset value msb lsb hex binary bodcfg bod configuration register ffc8h - - - - - - boicfg1 boicfg0 [2] clkcon clock control register ffdeh clkok - - - clkdbl fosc2 fosc1 fosc0 [3] rtcdath real-time clock data register high ffbfh 00 0000 0000 rtcdatl real-time clock data register low ffbeh 00 0000 0000
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 38 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 7.2 enhanced cpu the p89lpc9151/9161/9171 uses an enhanced 80c51 cpu which runs at six times the speed of standard 80c51 devices. a machine cycle consists of two cpu clock cycles, and most instructions execute in one or two machine cycles. 7.3 clocks 7.3.1 clock definitions the p89lpc9151/9161/9171 device has seve ral internal clocks as defined below: oscclk ? input to the divm clock divider. oscclk is selected from one of four clock sources (see figure 10 ) and can also be optionally divi ded to a slower frequency (see section 7.10 ? cclk modification: divm register ? ). remark: f osc is defined as the oscclk frequency. cclk ? cpu clock; output of the clock divider. there are two cclk cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four cclk cycles). rcclk ? the internal 7.373 mhz rc oscillator output. the clock doubler option, when enabled, provides an output frequency of 14.746 mhz. pclk ? clock for the various peripheral devices and is cclk ? 2 . 7.3.2 cpu clock (oscclk) the p89lpc9151/9161/9171 provides several user-selectable oscillator options in generating the cpu clock. this allows opti mization for a range of needs from high precision to lowest possible cost. these options are configured when the flash is programmed and incl ude an on-chip watchdog oscillator, an on-chip rc oscillator, or an external clock source. 7.4 clock output (p89lpc9171) the p89lpc9171 supports a user-selectable clock output function on the p0.7/clkout pin. this allows external devices to synchronize to the p89lpc9171. this output is enabled by the enclk bit in the trim register. the frequency of this clock output is 1 ? 2 that of the cclk. if th e clock output is not needed in idle mode, it may be turned off prior to entering idle, saving additional power. 7.5 on-chip rc oscillator option the p89lpc9151/9161/9171 has a 6-bit trim register that can be used to tune the frequency of the rc oscillator. during reset, the trim value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 mhz 1 % at room temperature. end-user applications can write to the trim register to adjust the on-chip rc oscillator to other frequencies. when the cl ock doubler option is enabled (ucfg2.7 = 1), the output frequency is 14.746 mhz. if cclk is 8 mhz or slower, the clklp sfr bit (auxr1.7) can be set to logic 1 to reduce power consumption. on reset, clklp is logic 0 allowing highest performance access. this bit can then be set in software if cclk is
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 39 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc running at 8 mhz or slower. when clock doubler option is enabled, boe1 bit (ucfg1.5) and boe0 bit (ucfg1.3) are required to hold the device in reset at power-up until v dd has reached its specified level. 7.6 watchdog oscillator option the watchdog has a separate osc illator which has a frequency of 400 khz, calibrated to 5 % at room temperature. this oscillator can be used to save power when a high clock frequency is not needed. 7.7 external clock input option in this configuration, the processor clock is derived from an external source driving the p0.5/clkin pin. the rate may be from 0 hz up to 18 mhz. when the frequency above 12 mhz, boe1 bit (ucfg1.5) and boe0 bit (ucfg1.3) are required to hold the device in reset at power-up until v dd has reached its specified level. remark: when using p0.5 as a clock input option, please make sure that p0.5 is configured as input only mode. 7.8 clock sources switch on the fly p89lpc9151/9161/9171 can implement clock source switch in any sources of watchdog oscillator, 7 mhz/14 mhz irc oscillator, or external cl ock input during co de is running. clkok bit in clkcon register is used to indicate the clock switch status. clkok is cleared when starting clock source switch and set when completed. notice that when clkok is ?0?, writing to clkc on register is not allowed. fig 10. block diagram of oscillator control 2 002aae574 rtc cpu wdt divm cclk oscclk xclk rcclk i 2 c-bus uart pclk timer 0 and timer 1 clkin rc oscillator watchdog oscillator pclk rcclk spi (P89LPC9161) rtcs1:0 adc1/dac1 clkout (7.3728 mhz/14.7456 mhz 1 %) (400 khz 5 %)
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 40 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 7.9 cclk wake-up delay the p89lpc9151/9161/9171 has an internal wa ke-up timer that delays the clock until it stabilizes depending on the clock source used. if the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 oscclk cycles plus 60 s to 100 s. if the clock source is the inter nal rc oscillator, the delay is 200 s to 300 s. if the clock source is watchdog osc illator or external cl ock, the delay is 32 oscclk cycles. 7.10 cclk modificati on: divm register the oscclk frequency can be divided down up to 510 times by configuring a dividing register, divm, to generate ccl k. this feature makes it poss ible to temporarily run the cpu at a lower rate, reducing power consumption. by dividing the clock, the cpu can retain the ability to respond to events that would not exit idle mode by executing its normal program at a lower rate. this can also allow by passing the oscillator start-up time in cases where power-down mode would otherwise be used. the value of divm may be changed by the program at any time with out interrupting code execution. 7.11 low power select the p89lpc9151/9161/9171 is designed to run at 18 mhz (cclk) maximum. however, if cclk is 8 mhz or slower, the clklp sfr bit (auxr1.7) can be set to logic 1 to lower the power consumption further. on any reset, clklp is logic 0 allowing highest performance access. this bit can then be set in software if cclk is running at 8 mhz or slower.
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 41 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 7.12 memory organization the various p89lpc9151/9161/9171 memory spaces are as follows: ? data 128 bytes of internal data memory space (00h :7fh) accessed via direct or indirect addressing, using instructions other than movx and movc. all or part of the stack may be in this area. ? idata indirect data. 256 bytes of internal data memory space (00h:ffh) accessed via indirect addressing using instructions othe r than movx and movc. all or part of the stack may be in this area. this area includes the data area and the 128 bytes immediately above it. ? sfr special function registers. selected cpu re gisters and peripheral control and status registers, accessible only via direct addressing. ? xdata ?external? data or auxiliary ram. duplicates the classic 80c51 64 kb memory space addressed via the movx instruction using th e dptr, r0, or r1. all or part of this space could be implemented on-chip. extended sfrs located in xdata. ? code 64 kb of code memory space, accessed as part of program execution and via the movc instruction. the p89lpc9151/9161/ 9171 has 2 kb on-chip code memory. 7.13 data ram arrangement the 256 bytes of on-chip ram are organized as shown in ta b l e 12 . 7.14 interrupts the p89lpc9151/9161/9171 uses a four priority level interrupt stru cture. this allows great flexibility in controlling the hand ling of the many in terrupt sources. the p89lpc9151/9171 supports 13 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port tx, serial port rx, combined serial port rx/tx, brownout detect, watchdog/rtc, i 2 c-bus, keyboard, comparators 1 and 2, a/d completion. the P89LPC9161 supports 13 interrupt sources: external interrupts 0, timers 0 and 1, serial port tx, serial port rx, combined serial port rx/tx, brownout detect, watchdog/rtc, i 2 c-bus, keyboard, comparators 1 and 2, spi, adc completion. each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers ien0 or ien1. the ien0 register also contains a global disable bit, ea, which disables all interrupts. table 12. on-chip data memory usages type data ram size (bytes) data memory that can be address ed directly and indirectly 128 idata memory that can be addressed indirectly 256
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 42 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc each interrupt source can be individually pr ogrammed to one of four priority levels by setting or clearing bits in the interrupt priority registers ip0, ip0h, ip1 and ip1h. an interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the highest priority interrupt service cannot be interrupted by any other interrupt so urce. if two requests of different priority levels are pending at the start of an instructio n, the request of higher priority level is serviced. if requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. this is called the arbitration ranking. note that the arbitration ranking is only used to resolve pending requests of the same priority level. 7.14.1 external interrupt inputs the p89lpc9151 and p89lpc9171 have two external interrupt inputs as well as the keypad interrupt function. the P89LPC9161 has one external interrupt input as well as the keypad interrupt function these external in terrupt inputs are identical to those present on the standard 80c51 microcontrollers. these external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit it1 or it0 in register tcon. in edge-triggered mode, if successive samples of the intn pin show a high in one cycle and a low in the next cycle, the interrupt request flag ien in tcon is set, causing an interrupt request. if an external interrupt is enabled when the p89lpc9151/9161/9171 is put into power-down or idle mode, the interrupt will c ause the processor to wake-up and resume operation. refer to section 7.17 ? power reduction modes ? for details.
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 43 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc fig 11. interrupt sources, interrupt enables, and power-down wake-up sources ie0 ex0 ie1 ex1 ec ea (ie0.7) cmf1 kbif ekbi boif ebo cmf2 tf0 et0 tf1 et1 es/esr ti and ri/ri ti est si ei2c spif espi ead enadci1 adci1 enbi1 bndi1 002aae575 rtcf ertc (rtccon.1) wdovf ( P89LPC9161 ) ewdrt wake-up (if in power-down) interrupt to cpu
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 44 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 7.15 i/o ports the p89lpc9151 has two i/o ports: port 0 and port 1. ports 0 and 1 are both 6-bit ports. the P89LPC9161/9171 has three i/o ports: port 0, port 1 and port 2. ports 0 is 5-bit ports in the P89LPC9161 and 7-bit ports in the p89lpc9171, port 1 is 5-bit ports in the P89LPC9161 and 6-bit ports in the p89lpc9171, port 2 is 4-bit ports in the P89LPC9161 and 1-bit port in the p89lpc9171. the exact number of i/o pins available depends upon the clock and reset options chosen, as shown in table 13 and ta b l e 14 [1] required for operation above 12 mhz. [1] required for operation above 12 mhz. 7.15.1 port configurations all but three i/o port pins on the p89lpc9151/9161/9171 may be configured by software to one of four types on a bit-by-bit basis. these are: quasi-bidirectional (standard 80c51 port outputs), push-pull, open drain, and inpu t-only. two configuration registers for each port select the output type for each port pin. 1. p1.5 ( rst ) can only be an input and cannot be configured. 2. p1.2 (scl/t0) and p1.3 (sda/ int0 ) may only be configured to be either input-only or open-drain. 7.15.1.1 quasi-bidirectional output configuration quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. this is possible beca use when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is driven table 13. number of i/o pins available (p89lpc9151) clock source reset option number of i/o pins (14-pin package) rc oscillator or watchdog oscillator no external reset (except during power-up) 12 external rst pin supported 11 external clock input no external reset (except during power-up) 11 external rst pin supported [1] 10 table 14. number of i/o pins available (P89LPC9161 and p89lpc9171) clock source reset option number of i/o pins (16-pin package) rc oscillator or watchdog oscillator no external reset (except during power-up) 14 external rst pin supported 13 external clock input no external reset (except during power-up) 13 external rst pin supported [1] 12
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 45 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc low, it is driven strongly and able to sink a fairly large current. these features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. the p89lpc9151/9161/9171 is a 3 v device, but the pins are 5 v tolerant. in quasi-bidirectional mode, if a user applies 5 v on the pin, there will be a current flowing from the pin to v dd , causing extra power consumpt ion. therefore, applying 5 v in quasi-bidirectional mode is discouraged. a quasi-bidirectional port pin has a schmitt tri gger input that also has a glitch suppression circuit. 7.15.1.2 open-drain output configuration the open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port la tch contains a logic 0. to be used as a logic output, a port configured in this manner must ha ve an external pull-up, typically a resistor tied to v dd . an open-drain port pin has a schmitt trigger input that also has a glitch suppression circuit. 7.15.1.3 input-only configuration the input-only port configuration has no output drivers. it is a schm itt trigger input that also has a glitch suppression circuit. 7.15.1.4 push-pull output configuration the push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. a push-pull port pin has a schmitt triggered input that also has a glitch suppression circuit. the p89lpc9151/9161/9171 device has high current source on eight pins in push-pull mode. see table 15 ? limiting values ? . 7.15.2 port 0 analog functions the p89lpc9151/9161/9171 incorporates two analog comparators. in order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. digital outputs are disabled by putting the port output into the input-only (high-impedance) mode. digital inputs on port 0 may be disabled through the use of the pt0ad register, bits 1:5. on any reset, pt0ad[1:5] defaults to logic 0s to enable digital functions. 7.15.3 additional port features after power-up, all pins are in input-only mode. please note that this is different from the lpc76x series of devices. ? after power-up, all i/o pins except p1.5, may be configured by software. ? pin p1.5 is input only. pins p1.2 and p1.3 are configurable for either input-only or open-drain.
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 46 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc every output on the p89lpc9151/9161/9171 has been designed to sink typical led drive current. however, there is a maximum total output current for all ports which must not be exceeded. please refer to table 16 ? static characteristics ? for detailed specifications. all ports pins that can function as an output ha ve slew rate controlled outputs to limit noise generated by quickly switching output sig nals. the slew rate is factory-set to approximately 10 ns rise and fall times. 7.16 power monitoring functions the p89lpc9151/9161/9171 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. this is accomplished with two hardware functions: power-on detect and brownout detect. 7.16.1 brownout detection the brownout detect function determines if the power supply voltage drops below a certain level. enhanced brownout detection has 3 independent functions: bod reset, bod interrupt and bod flash. bod reset is always on except in total power-down mode. it could not be disabled in software. bod interrupt may be enabled or disabled in software. bod flash is always on, except in power-down modes and could not be disabled in software. bod reset and bod interrupt, each has four trip voltage levels. boe1 bit (ucfg1.5) and boe0 bit (ucfg1.3) are used as trip point configuration bits of bod reset. boicfg1 bit and boicfg0 bit in register bodcfg are used as trip point configuration bits of bod interrupt. bod reset voltage shou ld be lower than bod interrupt trip point. bod flash is used for flash programming/erase protection and has only 1 trip voltage of 2.4 v. please refer to p89lpc9151/9161/9171 user manual for detail configurations. if brownout detection is enabled the brownout condition occurs when v dd falls below the brownout trip voltage and is negated when v dd rises above the brownout trip voltage. for correct activation of brownout detect, the v dd rise and fall times must be observed. please see table 16 ? static characteristics ? for specifications. 7.16.2 power-on detection the power-on detect has a function similar to the brownout detect, bu t is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. the pof flag in the rstsrc register is set to indicate an initial power-up condition. the pof flag will remain set until cleared by software. 7.17 power reduction modes the p89lpc9151/9161/9171 supports three different power reduction modes. these modes are idle mode, power-down mode, and total power-down mode. 7.17.1 idle mode idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. any enabled in terrupt source or reset may terminate idle mode.
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 47 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 7.17.2 power-down mode the power-down mode stops th e oscillator in order to mini mize power consumption. the p89lpc9151/9161/9171 exits power-down mode via any reset, or certain interrupts. in power-down mode, the power supply voltage may be reduced to the data retention supply voltage v ddr . this retains the ram contents at the point where power-down mode was entered. sfr contents are not guaranteed after v dd has been lowered to v ddr , therefore it is highly recommended to wake-up th e processor via reset in this case. v dd must be raised to within the operating range before the power-down mode is exited. some chip functions continue to operate and draw power during power-down mode, increasing the total power used during power-down. these include: brownout detect, watchdog timer, comparators (note that comparators can be powered down separately), and rtc/system timer. the intern al rc oscillator is disabled unless both the rc oscillator has been selected as the system clock and the rtc is enabled. 7.17.3 total power-down mode this is the same as power-do wn mode except that the brow nout detection circuitry and the voltage comparators are also disabled to conserve additional power. the internal rc oscillator is disabled unless bo th the rc oscillator has been se lected as the system clock and the rtc is enabled. if the internal rc o scillator is used to clock the rtc during power-down, there will be high power consumpti on. please use an exte rnal low frequency clock to achieve low power with the rtc running during power-down. 7.18 reset the p1.5/ rst pin can function as either a low-active reset input or as a digital input, p1.5. the reset pin enable (rpe) bit in ucfg1, when set to logic 1, enables the external reset input function on p1.5. when cleared, p1.5 may be used as an input pin. remark: during a power-up sequence, the rpe selection is overridden and this pin always functions as a reset input. an external circuit connected to this pin should not hold this pin low during a power-on sequence as this will keep the device in reset. after power-up this pin will fu nction as defined by the rpe bit. only a power-up reset will temporarily override the selection defined by rpe bit. other sources of reset will not override the rpe bit. note: during a power cycle, v dd must fall below v por before power is reapplied, in order to ensure a power-on reset (see table 16 ? static characteristics ? ). reset can be triggered from the following sources: ? external reset pin (during power-up or if user configured via ucfg1) ? power-on detect ? brownout detect ? watchdog timer ? software reset ? uart break character detect reset for every reset source, there is a flag in the reset register, rstsrc. the user can read this register to determine the most recent re set source. these flag bits can be cleared in software by writing a logic 0 to the corresponding bit. more than one flag bit may be set:
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 48 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc ? during a power-on reset, both pof and bof are set but the other flag bits are cleared. ? a watchdog reset is similar to a power-on reset, both pof and bof are set but the other flag bits are cleared. ? for any other reset, previously set flag bits that have no t been cleared will remain set. 7.18.1 reset vector following reset, the p89lpc9151 /9161/9171 will fetch instructio ns from either address 0000h or the boot address. the boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00h. the boot address will be used if a uart break reset oc curs, or the non -volatile boot status bit (bootstat.0) = 1. 7.19 timers/counters 0 and 1 the p89lpc9151/9161/9171 devices have two gen eral purpose counter/timers which are upward compatible with the standard 80c51 timer 0 and timer 1. an option to automatically toggle the t0 pin upon timer over flow has been added. in addition an option to toggle the t1 pin upon overflow has bee n added on the p89lpc9171. in the ?timer? function, the register is incremented every ma chine cycle. in the ?counter? function, the register of timer 0 is incremented in response to a 1-to-0 transition at its external input pin. this external input is sampled once every machine cycle. timer 0 has five operating modes (modes 0, 1, 2, 3 and 6). timer 1 has four operating modes (modes 0, 1, 2, and 3), except on the p89lpc9171 where timer 1 also has mode 6. modes 0, 1, 2 and 6 are the same for both timers/counters. mode 3 is different. 7.19.1 mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. in this mode, the timer register is configured as a 13-bit register. mode 0 operation is the same for timer 0 and timer 1. 7.19.2 mode 1 mode 1 is the same as mode 0, except that all 16 bits of the timer register are used. 7.19.3 mode 2 mode 2 configures the timer register as an 8-bit counter with automatic reload. mode 2 operation is the same for timer 0 and timer 1. 7.19.4 mode 3 when timer 1 is in mode 3 it is stopped. timer 0 in mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. when timer 1 is in mode 3 it can still be used by the serial port as a baud rate generator. 7.19.5 mode 6 in this mode, the corresponding timer can be changed to a pwm with a full period of 256 timer clocks.
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 49 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 7.19.6 timer overflow toggle output timer 0 (and timer 1 on the p89lpc9171) can be configured to automatically toggle a port output whenever a timer ov erflow occurs. the same device pins that are used for the t0 and t1 count inputs are al so used for the timer toggle ou tputs. the port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. 7.20 rtc/system timer the p89lpc9151/9161/9171 has a simple rtc that allows a user to continue running an accurate timer while the rest of the device is powered down. the rtc can be a wake-up or an interrupt source. the rtc is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. when it reaches all logic 0s, the counter will be reloaded again and the rtcf flag will be set. the clock source for this counter can be either the cpu clock (cclk) or the external clock input, provided that the external clock input is not being used as the cpu clock. if the external clock input is used as the cpu clo ck, then the rtc will use cclk as its clock source. only power-on reset will reset the rtc and its asso ciated sfrs to the default state. the 16-bit loadable counter portion of the rtc is readable by reading the rtcdatl and rtcdath registers. 7.21 uart the p89lpc9151/9161/9171 has an enhanced uart that is compatible with the conventional 80c51 uart except that timer 2 overflow cannot be used as a baud rate source. the p89lpc9151/9161/9171 does include an independent baud rate generator. the baud rate can be selected from the os cillator (divided by a constant), timer 1 overflow, or the independent baud rate generator. in addition to the baud rate generation, enhancements over the standard 80c51 uart include framing error detection, automatic address recognition, selectable doubl e buffering and several interrupt options. the uart can be operated in four modes: shift register, 8-bit uart, 9-bit uart, and cpu clock/32 or cpu clock/16. 7.21.1 mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted or received, lsb first. the baud rate is fixed at 1 ? 16 of the cpu clock frequency. 7.21.2 mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb first), and a stop bit (logic 1) . when data is received, the stop bit is stored in rb8 in special function register scon. th e baud rate is variable and is determined by the timer 1 overflow rate or the baud rate generator (described in section 7.21.5 ? baud rate generator and selection ? ). 7.21.3 mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logic 0), 8 data bits (lsb first), a programmable 9 th data bit, and a stop bit (logic 1). when data is transmitted, the 9 th data bit (tb8 in scon) can be assigned the value of logic 0 or logic 1.
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 50 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc or, for example, the parity bit (p, in the psw) could be moved into tb8. when data is received, the 9 th data bit goes into rb8 in special function register scon, while the stop bit is not saved. the baud rate is programmable to either 1 ? 16 or 1 ? 32 of the cpu clock frequency, as determined by the smod1 bit in pcon. 7.21.4 mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb first), a programmable 9 th data bit, and a stop bit (logic 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable and is determined by the timer 1 overflow rate or the baud rate generator (described in section 7.21.5 ? baud rate generator and selection ? ). 7.21.5 baud rate generator and selection the p89lpc9151/9161/9171 enhanced uart has an independent baud rate generator. the baud rate is determined by a baud-rate preprogrammed into the brgr1 and brgr0 sfrs which together form a 16-bit baud rate divisor value that works in a similar manner as timer 1 but is much more accurate. if the baud rate generator is used, timer 1 can be used for other timing functions. the uart can use either timer 1 or the baud rate generator output (see figure 12 ). note that timer t1 is further divided by 2 if the smod1 bit (pcon.7) is cleared. the independent baud rate generators use oscclk. 7.21.6 framing error framing error is reported in the status regist er (sstat). in addition, if smod0 (pcon.6) is logic 1, framing errors can be made available in scon.7 respectively. if smod0 is logic 0, scon.7 is sm0. it is recommended that sm0 and sm1 (scon.7:6) are set up when smod0 is logic 0. 7.21.7 break detect break detect is reported in the status re gister (sstat). a break is detected when 11 consecutive bits are sensed low. the brea k detect can be used to reset the device and force the device into isp mode. 7.21.8 double buffering the uart has a transmit double buffer that allo ws buffering of the next character to be written to sbuf while the firs t character is being transmitted. double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written be tween the start bit and the stop bit of the previous character. fig 12. baud rate so urces for uart (modes 1, 3) baud rate modes 1 and 3 sbrgs = 1 sbrgs = 0 smod1 = 0 smod1 = 1 timer 1 overflow (pclk-based) baud rate generator (cclk-based) 002aaa89 7 2
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 51 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc double buffering can be disabled. if disabled (dbmod, i.e., sstat.7 = 0), the uart is compatible with the conventio nal 80c51 uart. if enabled, t he uart allows writing to sbuf while the previous data is being shifted out. double buffering is only allowed in modes 1, 2 and 3. when operated in mode 0, double buffering must be disabled (dbmod = 0). 7.21.9 transmit interrupts with double buffering enabled (modes 1, 2 and 3) unlike the conventional uart, in double buffering mode, the ti interrupt is generated when the double buffer is ready to receive new data. 7.21.10 the 9 th bit (bit 8) in double buffering (modes 1, 2 and 3) if double buffering is disabled tb8 can be written before or after sbuf is written, as long as tb8 is updated some time before that bit is shifted out. tb8 must not be changed until the bit is shifted out, as in dicated by the ti interrupt. if double buffering is enabled, tb must be updated before sbuf is written, as tb8 will be double-buffered together with sbuf data. 7.22 i 2 c-bus serial interface the i 2 c-bus uses two wires (sda and scl) to transfer information between devices connected to the bus, and it has the following features: ? bidirectional data transfer between masters and slaves ? multi master bus (no central master) ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? the i 2 c-bus may be used for test and diagnostic purposes. a typical i 2 c-bus configuration is shown in figure 13 . the p89lpc9151/9161/9171 device provides a byte-oriented i 2 c-bus interface that supports data transfers up to 400 khz. fig 13. i 2 c-bus configuration other device with i 2 c-bus interface sda scl r p r p other device with i 2 c-bus interface p1.3/sda p1.2/scl p89lpc9151/9161/ 9171 i 2 c-bus 002aae576
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 52 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc fig 14. i 2 c-bus serial interface block diagram internal bus 002aaa89 9 address register comparator shift register 8 i2adr ack bit counter / arbitration and sync logic 8 i2dat timing and control logic serial clock generator cclk interrupt input filter output stage input filter output stage p1.3 p1.3/sda p1.2/scl p1.2 timer 1 overflow control registers and scl duty cycle registers i2con i2sclh i2scll 8 status decoder status bus status register 8 i2stat
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 53 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 7.23 spi (P89LPC9161) the P89LPC9161 provides another high-speed serial communication interface: the spi interface. spi is a full-duplex, high-spe ed, synchronous communication bus with two operation modes: master mode and slave mode. up to 3 mbit/s can be supported in either master mode or slave mode. it has a transfer completion flag and write collision flag protection. the spi interface has four pi ns: spiclk, mosi, miso and ss : ? spiclk, mosi and miso are typically ti ed together between two or more spi devices. data flows from master to slave on mosi (master out slave in) pin and flows from slave to master on miso (master in sl ave out) pin. the spic lk signal is output in the master mode and is input in the slave mode. if the spi system is disabled, i.e., spen (spctl.6) = 0 (reset value), these pins are configured for port functions. ? ss is the optional slave select pin. in a ty pical configuration, an spi master asserts one of its port pins to select one spi devi ce as the current slav e. an spi slave device uses its ss pin to determine whether it is selected. typical connections are shown in figure 16 through figure 18 . fig 15. spi block diagram 002aaa900 cpu clock divider by 4, 16, 64, 128 select clock logic spi control register read data buffer 8-bit shift register spi control spi status register spr1 spif wcol spr0 spi clock (master) pin control logic s m s m m s miso p2.3 mosi p2.2 spiclk p2.5 ss p2.4 spi interrupt request internal data bus ssig spen spen mstr dord mstr cpha cpol spr1 spr0 mstr spen clock
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 54 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 7.23.1 typical spi configurations fig 16. spi single master single slave configuration fig 17. spi dual device configuration, where either can be a master or a slave 002aaa90 1 master slave 8-bit shift register spi clock generator 8-bit shift register miso mosi spiclk port miso mosi spiclk ss 002aaa90 2 master slave 8-bit shift register spi clock generator spi clock generator 8-bit shift register miso mosi spiclk miso mosi spiclk ss ss
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 55 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 7.24 analog comparators two analog comparators are provided on th e p89lpc9151/9161/9171. input and output options allow use of the comparators in a num ber of different configurations. comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable inputs) is greater than the negative input (selectable from a pin or an internal reference voltage). otherwise the output is a zero. each comparator may be configured to cause an interrupt when the output value changes. comparator 1 may be output to a port pin. the overall connections to both comparators are shown in figure 19 . the comparators function to v dd = 2.4 v. when each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 s. the corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. when a comparator is disabled the comparator?s output, con, goes high. if the comparator output was low and then is disabled, the resulting transition of the comparator output from a lo w to high state will set the co mparator flag, cmfn. this will cause an interrupt if the comparator interrupt is enabled. the user should therefore disable the comparator interrupt prior to disabling the comparator. additionally, the user should clear the comparator flag, cmfn, after disabling the comparator. fig 18. spi single master multiple slaves configuration 002aaa90 3 master slave 8-bit shift register spi clock generator 8-bit shift register miso mosi spiclk port port miso mosi spiclk ss slave 8-bit shift register miso mosi spiclk ss
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 56 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 7.24.1 internal reference voltage an internal reference voltage generator may supply a default reference when a single comparator input pin is used. the value of the internal reference voltage, referred to as v ref(bg) , is 1.23 v 10 %. 7.24.2 comparator interrupt each comparator has an interrupt flag contained in its configuration register. this flag is set whenever the comparator output changes st ate. the flag may be polled by software or may be used to generate an interrupt. the two comparators use one common interrupt vector. if both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determi ne which comparator caused the interrupt. 7.24.3 comparators and power reduction modes either or both comparators may remain enabled when power-down or idle mode is activated, but both comparators are disabled automatically in total power-down mode. if a comparator interrupt is enabled (except in total power-down mode), a change of the comparator output state will generate an in terrupt and wa ke-up the processor. if the comparator output to a pin is enabled, the pin should be conf igured in the push-pull mode in order to obtain fast switch ing times while in power-down mo de. the reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. comparators consume power in power-down and idle modes, as well as in the normal operating mode. this fact sh ould be taken into account when system power consumption is an issue. to minimize power consumption, the user can disable the comparators via pcona.5, or put the device in total power-down mode. fig 19. comparator input and output connections comparator 1 cp1 cn1 (p0.4) cin1a (p0.3) cin1b (p0.5) cmpref v ref(bg) oe1 co1 cmf1 interrupt 002aae43 3 cmp1 (p0.6) ec cmf2 comparator 2 oe2 co2 cmp2 (p0.0) cp2 cn2 (p0.2) cin2a (p0.1) cin2b change detect change detect
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 57 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 7.25 kbi the keypad interrupt function (kbi) is intended primarily to allow a single interrupt to be generated when port 0 is equal to or not equal to a certain pattern. this function can be used for bus address recognition or keypad recognition. the user can configure the port via sfrs for different tasks. the keypad interrupt mask re gister (kbmask) is used to define which input pins connected to port 0 can trigger the interrupt. the keypad pattern register (kbpatn) is used to define a pattern that is compared to the value of port 0. the keypad interrupt flag (kbif) in the keypad interrup t control register (kbcon) is set when the condition is matched while the keypad interrupt function is active. an interrup t will be generated if enabled. the patn_sel bit in the keypad in terrupt control register (kbcon) is used to define equal or not-equal for the comparison. in order to use the keypad interrupt as an original kbi function like in 87lpc76x series, the user needs to set kbpatn = 0ffh and patn_sel = 1 (not equal), then any key connected to port 0 which is enabled by the kbmask re gister will cause t he hardware to set kbif and generate an interrupt if it has been enabled. the interrupt may be used to wake-up the cpu from id le or power-down modes. this feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. in order to set the flag and caus e an interrupt, th e pattern on port 0 must be held longer than six cclks. 7.26 watchdog timer the watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching it s terminal count. it consists of a programmable 12-bit prescaler, and an 8-bit down counter. the down counter is decremented by a tap taken from the prescaler. the clock source for the prescaler can be the pclk, or the nominal 400 khz watchdog oscillator. the watchdog timer can only be reset by a power-on reset. when the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. figure 20 shows the watchdog timer in watchdog mode. feeding the watchdog requires a two-byte sequence. if pclk is selected as the watchdog clock and the cpu is powered down, the watchdog is disabled. the watchdog timer has a time-out period that ranges from a few s to a few seconds. please refer to the p89lpc9151/9161/9171 user manual for more details.
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 58 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 7.27 additional features 7.27.1 software reset the srst bit in auxr1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. care should be taken when writing to auxr1 to avoid accidental software resets. 7.27.2 dual data pointers the dual data pointers (dptr) provides tw o different data poin ters to specify the address used with certain instructions. the d ps bit in the auxr1 register selects one of the two data pointers. bit 2 of auxr1 is permanently wired as a logic 0 so that the dps bit may be toggled (thereby switching data pointers) simply by incrementing the auxr1 register, without the possibilit y of inadvertently altering other bits in the register. 7.28 flash program memory 7.28.1 general description the p89lpc9151/9161/9171 flash memory prov ides in-circuit electrical erasure and programming. the flash can be erased, read, and written as bytes. the sector and page erase functions can eras e any flash sector (256 bytes) or page (16 bytes). the chip erase operation will erase th e entire program memory. ic p using standard commercial programmers is available. in addition, iap (i ap-lite) and byte-erase allows code memory to be used for non-volatile data storage. on-chip erase and write timing generation contribute to a user-friendly programming interface. the p89lpc9151/9161/9171 flash reliably stores memory contents even after 100,000 erase and program cycles. the cell is designed to optimize the erase and programming mechanisms. the (1) watchdog reset can also be caused by an in valid feed sequence, or by writing to wd con not immediately followed by a feed sequence. fig 20. watchdog timer in watchdog mode (wdte = 1) pre2 pre1 pre0 ? ? wdrun wdtof wdclk wdcon (a7h) control register prescaler 002aae577 shadow register for wdcon 8-bit down counter wdl (c1h) watchdog oscillator pclk 32 mov wfeed1, #0a5h mov wfeed2, #05ah reset (1)
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 59 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc p89lpc9151/9161/9171 uses v dd as the supply voltage to perform the program/erase algorithms. when voltage su pply is lower than 2.4 v, the bod flash is tripped and flash erase/program is blocked. 7.28.2 features ? programming and erase over the full operating voltage range. ? byte erase allows code memory to be used for data storage. ? read/programming/erase using icp. ? any flash program/erase operation in 2 ms. ? programming with industry-standard commercial programmers. ? programmable security for the code in the flash for each sector. ? 100,000 typical erase/program cycles for each byte. ? 10 year minimum data retention. 7.28.3 flash organization the program memory consists of eight 256- byte sectors on the p89lpc9151/9161/9171 devices. each sector can be further divided into 16-byte pages. in addition to sector erase, page erase, and byte erase, a 16-byte page register is inclu ded which allows from 1 byte to 16 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. in ad dition, erasing and reprogramming of user-programmable configuration bytes includ ing ucfg1, the boot status bit, and the boot vector is supported. 7.28.4 using flash as data storage the flash code memory array of this devi ce supports individual byte erasing and programming. any byte in the code memory array may be read using the movc instruction, provided that the sector containing the byte has not been secured (a movc instruction is not allowed to read code memory contents of a secured sector). thus any byte in a non-secured sector may be used for non-volatile data storage. 7.28.5 flash programming and erasing two different methods of erasing or programming of the flash are available. the flash may be programmed or erased in the end-user application (ia-lite) under control of the application?s firmware. another option is to use the icp mechanism. this icp system provides for programming through a serial clo ck/serial data interface. this device does not provide for direct verification of code memory contents. instead, this device provides a 32-bit crc result on either a sector or the entire user code space. remark: when voltage supply is lower than 2.4 v, the bod flash is tripped and flash erase/program is blocked. 7.28.6 icp icp is performed without removing the microcont roller from the system. the icp facility consists of internal hardw are resources to facilitate remote programming of the p89lpc9151/9161/9171 through a two-wire serial inte rface. the nxp icp facility has made in-circuit programming in an embedded application - using commercially available programmers - possible with a minimum of addi tional expense in components and circuit
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 60 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc board area. the icp function uses five pins. only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. additional details may be found in the p89lpc9151/9161/9171 user manual . 7.28.7 iap-lite iap-lite is performed in the application under the control of the microcontroller?s firmware. the iap facility consists of internal hardware resources to facilitate pr ogramming and erasing. the iap-lite operations are accomplished through the use of four sfrs consisting of a control/status register, a data register, and two address registers. additional details may be found in the p89lpc9151/9161/9171 user?s manual. 7.29 user configuration bytes some user-configurable features of the p89lpc9151/9161/9171 must be defined at power-up and therefore cannot be set by the program after start of execution. these features are configured through the use of the flash byte ucfg1 and ucfg2. please see the p89lpc9151/9161/9171 user?s manual for additional details. 7.30 user sector security bytes there are 8 user sector security bytes on the p89lpc9151/9161/9171. each byte corresponds to one sector. please see the p89lpc9151/9161/9171 user manual for additional details. 8. adc 8.1 general description the p89lpc9151/9161/9171 devices have a single 8-bit, 4-channel multiplexed analog-to-digital converter. a block diagram of the a/d converter is shown in figure 21 . the a/d consists of a 4-input multiplexer wh ich feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. the control logic in combination with the sar drives a digital-to-analog converter which provides the other input to the comparator. the output of the comparator is fed to the sar. 8.2 features ? 8-bit, 4-channel multiplexed input, successive approximation adc. ? four a/d result registers. ? six operating modes: ? fixed channel, single conversion mode. ? fixed channel, continuous conversion mode. ? auto scan, single conversion mode. ? auto scan, continuous conversion mode. ? dual channel, continuous conversion mode. ? single step mode. ? three conversion start modes: ? timer triggered start. ? start immediately.
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 61 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc ? edge triggered. ? 8-bit conversion time of 1.61 s at an a/d clock of 8.0 mhz. ? interrupt or polled operation. ? boundary limits interrupt. ? dac output to a port pin with high output impedance. ? clock divider. ? power-down mode. 8.3 block diagram 8.4 adc operating modes 8.4.1 fixed channel, single conversion mode a single input channel can be selected fo r conversion. a single conversion will be performed and the result placed in the result register which corresponds to the selected input channel. an interrupt, if enabled, will be generated afte r the conversion completes. 8.4.2 fixed channel, continuous conversion mode a single input channel can be selected for continuous conversion. the results of the conversions will be sequentially placed in the fo ur result register. the user may select whether an interrupt can be generated after ev ery four conversions. additional conversion results will again cycle through the four result register, over writing the previous results. continuous conversions continue until terminated by the user. 8.4.3 auto scan, single conversion mode any combination of the four input channels can be selected for conversion. a single conversion of each selected in put will be performed and the re sult placed in the result register which corresponds to th e selected input channel. an in terrupt, if en abled, will be generated after all selected channels have be en converted. if only a single channel is selected this is equivalent to sing le channel, single conversion mode. 8.4.4 auto scan, continuous conversion mode any combination of the four input channels ca n be selected for conversion. a conversion of each selected input will be performed and th e result placed in the result register which corresponds to the sele cted input channel. an interrupt, if enabled, will be generated after fig 21. adc block diagram sar 002aaa78 3 8 cclk comp dac1 control logic input mux
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 62 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc all selected channels have been converted. the process will re peat starting with the first selected channel. additional conversion results will again cycle through the four result register pairs, overwriting the previous results. continuous conversions continue until terminated by the user. 8.4.5 dual channel, continuous conversion mode this is a variation of the auto scan contin uous conversion mode where conversion occurs on two user-selectable inputs. the result of t he conversion of the first channel is placed in the result register, ad1dat0. the result of th e conversion of the second channel is placed in result register, ad1dat1. the first channel is again converted and its result stored in ad1dat2. the second channel is again converted and its result placed in ad1dat3. an interrupt is generated, if enabled, after every set of four conversions (two conversions per channel). 8.4.6 single step mode this special mode allows ?s ingle-stepping? in an auto scan conversion mode. any combination of the four input channels can be selected for conversion. after each channel is converted, an interrupt is generated, if enabled, and the a/d waits for the next start condition. may be used with any of the start modes. 8.5 conversion start modes 8.5.1 timer triggered start an a/d conversion is started by the overflow of timer 0. once a conversion has started, additional timer 0 triggers are ignored until the conversion has completed. the timer triggered start mode is avail able in all adc operating modes. 8.5.2 start immediately programming this mode immediately starts a conv ersion. this start mode is available in all adc operating modes. 8.5.3 edge triggered an a/d conversion is started by rising or falling edge of p1.4. once a conversion has started, additional edge triggers are ignored until the conversion has completed. the edge triggered start mode is avail able in all adc operating modes. 8.6 boundary limits interrupt each of the a/d converters has both a high and low boundary limit register. the user may select whether an interrupt is generated when the conversion result is within (or equal to) the high and low boundary limits or when the conversion result is outside the boundary limits. an interrupt will be genera ted, if enabled, if the result meets the sele cted interrupt criteria. the boundary limit may be disabled by clearing the boundary limit interrupt enable. an early detection mechanism exists when the interrupt criter ia has been selected to be outside the boundary limits. in this case, afte r the four msbs have been converted, these four bits are compared with the four msbs of the boundary high and low registers. if the four msbs of the conversion meet the interrupt criteria (i.e., outside the boundary limits) an interrupt will be generated, if enabled. if the four msbs do not meet the interrupt
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 63 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc criteria, the boundary limits will again be compared after all 8 bits have been converted. the boundary status register (bndsta0) fl ags the channels which caused a boundary interrupt. 8.7 dac output to a port pin with high output impedance the dac block of adc1 can be output to a port pin. in this mode, the ad1dat3 register is used to hold the value fed to the dac. afte r a value has been written to the dac (written to ad1dat3), the dac output will appear on the channel 3 pin. 8.8 clock divider the adc requires that its internal clock source be in the range of 320 khz to 8 mhz to maintain accuracy. a programmable clo ck divider that divides the clock from 1 to 8 is provided for this purpose. 8.9 power-down and idle mode in idle mode the a/c converte r, if enabled, will continue to function and can cause the device to exit idle mode when the conversion is completed if the a/d interrupt is enabled. in power-down mode or total power-down mode, the a/d does not function. if the a/d is enabled, it will consume power. power ca n be reduced by disabling the a/d.
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 64 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 9. limiting values [1] the following applies to table 15 : a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over ambient temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. [2] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k series resistor. table 15. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit t amb(bias) bias ambient temperature ? 55 +125 c t stg storage temperature ? 65 +150 c i oh(i/o) high-level output current per input/output pin - 20 ma i ol(i/o) low-level output current per input/output pin - 20 ma i i/otot(max) maximum total input/output current - 100 ma v xtal crystal voltage on xtal1, xtal2; pin to v ss - v dd + 0.5 v v n voltage on any other pin except xtal1, xtal2; pin to v ss ? 0.5 +5.5 v p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 w v esd electrostatic discharge voltage human body model; all pins [2] ? 3000 +3000 charged device model; all pins ? 700 +700 fig 22. frequency versus supply voltage v dd (v) 002aae35 1 system frequency (mhz) 2.4 18 12 2.7 3.6 3.3 3.0
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 65 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 10. static characteristics table 16. static characteristics v dd = 2.4 v to 3.6 v unless otherwise specified. t amb = ? 40 c to +85 c for industrial applications, unless otherwise specified. symbol parameter conditions min typ [1] max unit i dd(oper) operating supply current v dd = 3.6 v; f osc = 12 mhz [2] - 10 15 ma v dd = 3.6 v; f osc = 18 mhz [2] - 14 23 ma i dd(idle) idle mode supply current v dd = 3.6 v; f osc = 12 mhz [3] - 3.25 5 ma v dd = 3.6 v; f osc = 18 mhz [3] - 5 7 ma i dd(pd) power-down mode supply current v dd = 3.6 v; voltage comparators powered down [4] - 20 40 a i dd(tpd) total power-down mode supply current v dd = 3.6 v [5] - 1 5 a (dv/dt) r rise rate of v dd ; to ensure por signal 5 - 5000 v/s v ddr data retention supply voltage 1.5 - - v v th(hl) high-low threshold voltage except scl, sda 0.22v dd 0.4v dd - v v il low-level input voltage scl, sda only ? 0.5 - 0.3v dd v v th(lh) low-high threshold voltage except scl, sda - 0.6v dd 0.7v dd v v ih high-level input voltage scl, sda only 0.7v dd - 5.5 v v hys hysteresis voltage port 1 - 0.2v dd - v v ol low-level output voltage i ol = 20 ma; v dd = 2.4 v to 3.6 v all ports, all modes except high-z [6] - 0.6 1.0 v i ol = 3.2 ma; v dd = 2.4 v to 3.6 v all ports, all modes except high-z [6] - 0.2 0.3 v v oh high-level output voltage i oh = ? 20 a; v dd = 2.4 v to 3.6 v; all ports, quasi-bidirectional mode v dd ? 0.3 v dd ? 0.2 - v i oh = ? 3.2 ma; v dd = 2.4 v to 3.6 v; all ports, push-pull mode v dd ? 0.7 v dd ? 0.4 - v i oh = ? 10 ma; v dd = 2.4 v to 3.6 v; all ports, push-pull mode - 3.2 - v v n voltage on any other pin except v dd ; with respect to v ss [7] ? 0.5 - +5.5 v c iss input capacitance [8] - - 15 pf i il low-level input current v i = 0.4 v [9] - - ? 80 a i li input leakage current v i = v il , v ih , or v th(hl) [10] - - 1 a i thl high-low transition current all ports; v i = 1.5 v at v dd = 3.6 v [11] ? 30 - ? 450 a
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 66 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc [1] typical ratings are not guaranteed. the va lues listed are at room temperature, 3 v. [2] the i dd(oper) specification is measured using an external clock with code while(1) {} executed from on-chip flash. [3] the i dd(idle) specification is measured using an external clock with no active peripherals, with the following func tions disabled: real-time clock and watchdog timer. [4] the i dd(pd) specification is measured usi ng internal rc oscillator with the following func tions disabled: comparator s, real-time clock, an d watchdog timer. [5] the i dd(tpd) specification is measured using an exte rnal clock with the follow ing functions disabled: comp arators, real-time clock, brownout detect, and watchdog timer. [6] see section 9 ? limiting values ? for steady state (non-transient) limits on i ol or i oh . if i ol /i oh exceeds the test condition, v ol /v oh may exceed the related specification. [7] this specification can be applied to pins which have a/d input or analog comparator input functions when the pin is not bein g used for those analog functions. when the pin is being used as an analog i nput pin, the maximum voltage on the pin must be limited to 4. 0 v with respect to v ss . [8] pin capacitance is characterized but not tested. [9] measured with port in quasi-bidirectional mode. [10] measured with port in high-impedance mode. [11] port pins source a transition current when used in quasi-bidirectional mode and exte rnally driven from logic 1 to logic 0. this current is highest when v i is approximately 2 v. r rst_n(int) internal pull-up resistance on pin rst pin rst 10 - 30 k v ref(bg) band gap reference voltage 1.11 1.23 1.34 v tc bg band gap temperature coefficient - 10 20 ppm/ c table 16. static characteristics ?continued v dd = 2.4 v to 3.6 v unles s otherwise specified. t amb = ? 40 c to +85 c for industrial applications, unless otherwise specified. symbol parameter conditions min typ [1] max unit
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 67 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 10.1 current characteristics note: the graphs provided are a statistical summary based on a limited number of samples and only for information purposes. t he performance characteristics listed are not tested or guaranteed. test conditions: normal mode, code while(1) {} executed from on- chip flash; using an external clock. fig 23. i dd(oper) versus frequency at +25 c test conditions: normal mode, code while(1) {} executed from on- chip flash; using an external clock. fig 24. i dd(oper) versus frequency at ? 40 c v dd (v) 2.4 3.6 3.2 2.8 002aae363 8 4 12 16 i dd (ma) 0 18 mhz 12 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz 32 khz v dd (v) 2.4 3.6 3.2 2.8 002aae364 8 4 12 16 i dd (ma) 0 18 mhz 12 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz 32 khz
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 68 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc test conditions: normal mode, code while(1) {} executed from on- chip flash; using an external clock. fig 25. i dd(oper) versus frequency at +85 c test conditions: idle mode entered executing code fr om on-chip flash; using an external clock with no active peripherals, with the following functi ons disabled: real-time clock and watchdog timer. fig 26. i dd(idle) versus frequency at +25 c v dd (v) 2.4 3.6 3.2 2.8 002aae365 8 4 12 16 i dd (ma) 0 18 mhz 12 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz 32 khz v dd (v) 2.4 3.6 3.2 2.8 002aae366 2.0 3.0 1.0 4.0 5.0 i dd (ma) 0.0 18 mhz 12 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz 32 khz
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 69 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc test conditions: idle mode entered executing code fr om on-chip flash; using an external clock with no active peripherals, with the following functi ons disabled: real-time clock and watchdog timer. fig 27. i dd(idle) versus frequency at ? 40 c test conditions: idle mode entered executing code fr om on-chip flash; using an external clock with no active peripherals, with the following functi ons disabled: real-time clock and watchdog timer. fig 28. i dd(idle) versus frequency at +85 c v dd (v) 2.4 3.6 3.2 2.8 002aae367 2.0 3.0 1.0 4.0 5.0 i dd (ma) 0.0 18 mhz 12 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz 32 khz v dd (v) 2.4 3.6 3.2 2.8 002aae368 2.0 3.0 1.0 4.0 5.0 i dd (ma) 0.0 18 mhz 12 mhz 8 mhz 6 mhz 4 mhz 2 mhz 1 mhz 32 khz
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 70 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc test conditions: power-down mode, using internal rc oscillator with the following functions disabled: comparators, real-t ime clock, and watchdog timer. (1) +85 c (2) +25 c (3) ? 40 c fig 29. i dd(pd) versus v dd test conditions: total power-down mode, using inte rnal rc oscillator with the following functions disabled: comparators, brownout detect, real-time clock, and watchdog timer. (1) +85 c (2) ? 40 c (3) +25 c fig 30. i dd(tpd) versus v dd v dd (v) 2.4 3.6 3.2 2.8 002aae369 14.0 16.0 12.0 18.0 20.0 i dd ( a) 10.0 (2) (3) (1) v dd (v) 2.4 3.6 3.2 2.8 002aae370 0.4 0.8 1.2 i dd ( a) 0.0 (1) (2) (3)
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 71 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 10.2 internal rc/watchdog os cillator characteristics note: the graphs provided are a statistical summary based on a limited number of samples and only for information purposes. t he performance characteristics listed are not tested or guaranteed. central frequency of internal rc oscillator = 7.3728 mhz fig 31. average internal rc oscillator frequency versus v dd at +25 c note: central frequency of internal rc oscillator = 7.3728 mhz fig 32. average internal rc oscillator frequency versus v dd at ? 40 c v dd (v) 2.4 3.6 3.2 2.8 002aae344 0 ? 0.1 0.1 0.2 frequency deviation (%) ? 0.2 v dd (v) 2.4 3.6 3.2 2.8 002aae346 0 ? 0.1 0.1 0.2 frequency deviation (%) ? 0.2
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 72 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc central frequency of internal rc oscillator = 7.3728 mhz fig 33. average internal rc oscillator frequency versus v dd at +85 c central frequency of watchdog oscillator = 400 khz fig 34. average watchdog oscillator frequency versus v dd at +25 c v dd (v) 2.4 3.6 3.2 2.8 002aae347 ? 0.2 ? 0.4 0 0.2 frequency deviation (%) ? 0.6 v dd (v) 2.4 3.6 3.2 2.8 002aae348 0.5 ? 0.5 1.5 2.5 frequency deviation (%) ? 1.5
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 73 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc central frequency of watchdog oscillator = 400 khz fig 35. average watchdog oscillator frequency versus v dd at ? 40 c central frequency of watchdog oscillator = 400 khz fig 36. average watchdog oscillator frequency versus v dd at +85 c v dd (v) 2.4 3.6 3.2 2.8 002aae349 ? 1.5 ? 2.5 ? 0.5 0.5 frequency deviation (%) ? 3.5 v dd (v) 2.4 3.6 3.2 2.8 002aae350 ? 0.5 ? 1.5 0.5 1.5 frequency deviation (%) ? 2.5
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 74 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 10.3 bod characteristics [1] typical ratings are not guaranteed. the va lues listed are at room temperature, 3 v. table 17. bod static characteristics v dd = 2.4 v to 3.6 v unless otherwise specified. t amb = ? 40 c to +85 c for industrial applications, unless otherwise specified. symbol parameter conditions min typ [1] max unit bod interrupt v trip trip voltage falling stage boicfg1, boicfg0 = 01 2.25 - 2.55 v boicfg1, boicfg0 = 10 2.60 - 2.80 v boicfg1, boicfg0 = 11 3.10 - 3.40 v rising stage boicfg1, boicfg0 = 01 2.30 - 2.60 v boicfg1, boicfg0 = 10 2.70 - 2.90 v boicfg1, boicfg0 = 11 3.15 - 3.45 v bod reset v trip trip voltage falling stage boe1, boe0 = 01 2.10 - 2.30 v boe1, boe0 = 10 2.25 - 2.55 v boe1, boe0 = 11 2.80 - 3.20 v rising stage boe1, boe0 = 01 2.20 - 2.40 v boe1, boe0 = 10 2.30 - 2.60 v boe1, boe0 = 11 2.90 - 3.30 v bod eeprom/flash v trip trip voltage falling stage 2.25 - 2.55 v rising stage 2.30 - 2.60 v fig 37. bod interrupt/reset characteristics v dd v trip 002aae352 (bof/boif set by hardware) (bof/boif can be cleared in software) bof/boif
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 75 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 11. dynamic characteristics table 18. dynamic characteristics (12 mhz) v dd = 2.4 v to 3.6 v unless otherwise specified. t amb = ? 40 c to +85 c for industrial applications, unless otherwise specified. [1] [2] symbol parameter conditions variable clock f osc = 12 mhz unit min max min max f osc(rc) internal rc oscillator frequency nominal f = 7.3728 mhz trimmed to 1 % at t amb = 25 c; clock doubler option = off (default) 7.189 7.557 7.189 7.557 mhz nominal f = 14.7456 mhz; clock doubler option = on, v dd = 2.7 v to 3.6 v 14.378 15.114 14.378 15.114 mhz f osc(wd) internal watchdog oscillator frequency t amb = 25 c 380 420 380 420 khz f osc oscillator frequency 0 12 - - mhz t cy(clk) clock cycle time see figure 38 83 - - - ns f clklp low-power select clock frequency 0 8 - - mhz glitch filter t gr glitch rejection time p1.5/ rst pin - 50 - 50 ns any pin except p1.5/ rst - 15 - 15 ns t sa signal acceptance time p1.5/ rst pin 125 - 125 - ns any pin except p1.5/ rst 50 - 50 - ns external clock t chcx clock high time see figure 38 33 t cy(clk) ? t clcx 33 - ns t clcx clock low time see figure 38 33 t cy(clk) ? t chcx 33 - ns t clch clock rise time see figure 38 - 8 - 8 ns t chcl clock fall time see figure 38 - 8 - 8 ns shift register (uart mode 0) t xlxl serial port clock cycle time see figure 39 16t cy(clk) - 1333 - ns t qvxh output data set-up to clock rising edge time see figure 39 13t cy(clk) - 1083 - ns t xhqx output data hold after clock rising edge time see figure 39 - t cy(clk) + 20 - 103 ns t xhdx input data hold after clock rising edge time see figure 39 - 0 - 0 ns t xhdv input data valid to clock rising edge time see figure 39 150 - 150 - ns spi interface f spi spi operating frequency slave 0 cclk ? 6 0 2.0 mhz master - cclk ? 4 - 3.0 mhz
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 76 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc [1] parameters are valid over operating tem perature range unless otherwise specified. [2] parts are tested to 2 mhz, but are guaranteed to operate down to 0 hz. t spicyc spi cycle time see figure 40 , 41 , 42 , 43 slave 6 ? cclk - 500 - ns master 4 ? cclk - 333 - ns t spilead spi enable lead time see figure 42 , 43 slave 250 - 250 - ns t spilag spi enable lag time see figure 42 , 43 slave 250 - 250 - ns t spiclkh spiclk high time see figure 40 , 41 , 42 , 43 master 2 ? cclk - 165 - ns slave 3 ? cclk - 250 - ns t spiclkl spiclk low time see figure 40 , 41 , 42 , 43 master 2 ? cclk - 165 - ns slave 3 ? cclk - 250 - ns t spidsu spi data set-up time see figure 40 , 41 , 42 , 43 100 - 100 - ns master or slave t spidh spi data hold time see figure 40 , 41 , 42 , 43 100 - 100 - ns master or slave t spia spi access time see figure 42 , 43 slave 0 120 0 120 ns t spidis spi disable time see figure 42 , 43 slave 0 240 - 240 ns t spidv spi enable to output data valid time see figure 40 , 41 , 42 , 43 slave - 240 - 240 ns master - 167 - 167 ns t spioh spi output data hold time see figure 40 , 41 , 42 , 43 0 - 0 - ns t spir spi rise time see figure 40 , 41 , 42 , 43 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns t spif spi fall time see figure 40 , 41 , 42 , 43 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns table 18. dynamic characteristics (12 mhz) ?continued v dd = 2.4 v to 3.6 v unles s otherwise specified. t amb = ? 40 c to +85 c for industrial applications, unless otherwise specified. [1] [2] symbol parameter conditions variable clock f osc = 12 mhz unit min max min max
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 77 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc table 19. dynamic characteristics (18 mhz) v dd = 3.0 v to 3.6 v unless otherwise specified. t amb = ? 40 c to +85 c for industrial applications, unless otherwise specified. [1] [2] symbol parameter conditions variable clock f osc = 18 mhz unit min max min max f osc(rc) internal rc oscillator frequency nominal f = 7.3728 mhz trimmed to 1 % at t amb = 25 c; clock doubler option = off (default) 7.189 7.557 7.189 7.557 mhz nominal f = 14.7456 mhz; clock doubler option = on 14.378 15.114 14.378 15.114 mhz f osc(wd) internal watchdog oscillator frequency t amb = 25 c 380 420 380 420 khz f osc oscillator frequency 0 18 - - mhz t cy(clk) clock cycle time see figure 38 55 - - - ns f clklp low-power select clock frequency 0 8 - - mhz glitch filter t gr glitch rejection time p1.5/ rst pin - 50 - 50 ns any pin except p1.5/ rst - 15 - 15 ns t sa signal acceptance time p1.5/ rst pin 125 - 125 - ns any pin except p1.5/ rst 50 - 50 - ns external clock t chcx clock high time see figure 38 22 t cy(clk) ? t clcx 22 - ns t clcx clock low time see figure 38 22 t cy(clk) ? t chcx 22 - ns t clch clock rise time see figure 38 - 5 - 5 ns t chcl clock fall time see figure 38 - 5 - 5 ns shift register (uart mode 0) t xlxl serial port clock cycle time see figure 39 16t cy(clk) - 888 - ns t qvxh output data set-up to clock rising edge time see figure 39 13t cy(clk) - 722 - ns t xhqx output data hold after clock rising edge time see figure 39 - t cy(clk) + 20 - 75 ns t xhdx input data hold after clock rising edge time see figure 39 - 0 - 0 ns t xhdv input data valid to clock rising edge time see figure 39 150 - 150 - ns spi interface f spi spi operating frequency slave 0 cclk ? 6 0 3.0 mhz master - cclk ? 4 - 4.5 mhz t spicyc spi cycle time see figure 40 , 41 , 42 , 43 slave 6 ? cclk - 333 - ns master 4 ? cclk - 222 - ns
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 78 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc [1] parameters are valid over operating tem perature range unless otherwise specified. [2] parts are tested to 2 mhz, but are guaranteed to operate down to 0 hz. t spilead spi enable lead time see figure 42 , 43 slave 250 - 250 - ns t spilag spi enable lag time see figure 42 , 43 slave 250 - 250 - ns t spiclkh spiclk high time see figure 40 , 41 , 42 , 43 slave 3 ? cclk - 167 - ns master 2 ? cclk - 111 - ns t spiclkl spiclk low time see figure 40 , 41 , 42 , 43 slave 3 ? cclk - 167 - ns master 2 ? cclk - 111 - ns t spidsu spi data set-up time see figure 40 , 41 , 42 , 43 master or slave 100 - 100 - ns t spidh spi data hold time see figure 40 , 41 , 42 , 43 master or slave 100 - 100 - ns t spia spi access time see figure 42 , 43 slave 0 80 0 80 ns t spidis spi disable time see figure 42 , 43 slave 0 160 - 160 ns t spidv spi enable to output data valid time see figure 40 , 41 , 42 , 43 slave - 160 - 160 ns master - 111 - 111 ns t spioh spi output data hold time see figure 40 , 41 , 42 , 43 0 - 0 - ns t spir spi rise time see figure 40 , 41 , 42 , 43 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns t spif spi fall time see figure 40 , 41 , 42 , 43 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns table 19. dynamic characteristics (18 mhz) ?continued v dd = 3.0 v to 3.6 v unles s otherwise specified. t amb = ? 40 c to +85 c for industrial applications, unless otherwise specified. [1] [2] symbol parameter conditions variable clock f osc = 18 mhz unit min max min max
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 79 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 11.1 waveforms fig 38. external clock timing (wit h an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa90 7 fig 39. shift register mode timing 0 1234567 valid valid valid valid valid valid valid valid t xlxl 002aaa90 6 set ti set ri t xhqx t qvxh t xhdv t xhdx clock output data write to sbuf input data clear ri fig 40. spi master timing (cpha = 0) t spicyc t spiclkh t spiclkh t spiclkl t spiclkl master lsb/msb out master msb/lsb out t spidh t spidsu t spif t spioh t spidv t spir t spidv t spif t spir t spif t spir ss spiclk (cpol = 0) (output) 002aaa908 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 80 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc fig 41. spi master timing (cpha = 1) t spicyc t spiclkl t spiclkl t spiclkh t spiclkh master lsb/msb out master msb/lsb out t spidh t spidsu t spif t spioh t spidv t spir t spidv t spif t spif t spir t spir ss spiclk (cpol = 0) (output) 002aaa909 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in fig 42. spi slave timing (cpha = 0) t spicyc t spiclkh t spiclkh t spiclkl t spiclkl t spilead t spilag t spidsu t spidh t spidh t spidsu t spidsu t spif t spia t spioh t spidis t spir slave msb/lsb out msb/lsb in lsb/msb in slave lsb/msb out t spidv t spioh t spioh t spidv t spir t spir t spif t spif ss spiclk (cpol = 0) (input) 002aaa910 spiclk (cpol = 1) (input) miso (output) mosi (input) not defined
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 81 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 12. other characteristics 12.1 comparator electr ical characteristics [1] this parameter is characterized, but not tested in production. fig 43. spi slave timing (cpha = 1) 002aaa911 t spicyc t spiclkh t spiclkh t spiclkl t spilead t spiclkl t spilag t spidsu t spidsu t spidh t spidh t spif t spir t spir t spia t spioh t spioh t spioh t spidis slave msb/lsb out not defined msb/lsb in lsb/msb in slave lsb/msb out t spidv t spidv t spidv t spir t spif t spif ss spiclk (cpol = 0) (input) spiclk (cpol = 1) (input) miso (output) mosi (input) table 20. comparator electrical characteristics v dd = 2.4 v to 3.6 v, unless otherwise specified. t amb = ? 40 c to +85 c for industrial applications, unless otherwise specified. symbol parameter conditions min typ max unit v io input offset voltage - - 20 mv v ic common-mode input voltage 0 - v dd ? 0.3 v cmrr common-mode rejection ratio [1] - - ? 50 db t res(tot) total response time - 250 500 ns t (ce-ov) chip enable to output valid time - - 10 s i li input leakage current 0 v < v i < v dd - - 1 a
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 82 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 12.2 adc electrical characteristics table 21. adc/temperature senso r electrical characteristics v dd = 2.4 v to 3.6 v, unless otherwise specified. t amb = ? 40 c to +85 c for industrial applications, unless otherwise specified. all limits valid for an external source impedance of less than 10 k . symbol parameter conditions min typ max unit v dda(adc) adc analog supply voltage v ssa analog ground voltage v ia analog input voltage v ss ? 0.2 - v dd + 0.2 v c ia analog input capacitance - - 15 pf e d differential linearity error - - 1 lsb e l(adj) integral non-linearity - - 1 lsb e o offset error - - 2 lsb e g gain error - - 1 % e u(tot) total unadjusted error - - 2 lsb m ctc channel-to-channel matching - - 1 lsb ct(port) crosstalk between port inputs 0 khz to 100 khz - - ? 60 db sr in input slew rate - - 100 v/ms t cy(adc) adc clock cycle time 111 - 2000 ns t adc adc conversion time adc enabled - - 13t cy(adc) s fig 44. adc conversion timing adc_clk serial_data_out d7 d6 d5 d4 d3 d2 d1 d0 12345678910111213 clk adcdata_reg adcdata 002aae371 start trigger
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 83 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc (1) example of an actual transfer curve. (2) the ideal transfer curve. fig 45. adc characteristics 002aae372 255 254 253 252 (2) (1) 256 253 254 255 7 123456 7 6 5 4 3 2 1 0 1 lsb (ideal) code out v dda ? v ssa 256 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 84 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 13. package outline fig 46. tssop14 package outline (sot402-1) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402 -1 a max. 1.1 pin 1 index
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 85 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc fig 47. tssop16 package outline (sot403-1) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403 -1 a max. 1.1 pin 1 index
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 86 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 14. abbreviations table 22. abbreviations acronym description adc analog to digital converter bod brownout detection cpu central processing unit dac digital to analog converter eeprom electrically erasable programmable read-only memory eprom erasable programmable read-only memory emi electromagnetic interference irc internal rc lsb least significant bit msb most significant bit pll phase-locked loop pwm pulse width modulator ram random access memory rc resistance-capacitance rtc real-time clock sar successive approximation register scl serial clock line sda serial data line sfr special function register spi serial peripheral interface uart universal asynchronous receiver/transmitter
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 87 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 15. revision history table 23. revision history document id release date data sheet status change notice supersedes p89lpc9151_61_71_2 20100209 product data sheet - p89lpc9151_61_71_1 modifications: ? changed data sheet status to "product data sheet". p89lpc9151_61_71_1 20091209 preliminary data sheet - -
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 88 of 91 nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 16.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer?s third party customer(s) (hereinafter both referred to as ?application?). it is customer?s sole responsibility to check whether the nxp semiconductors product is suitable and fit for the application planned. customer has to do all necessary testing for the application in order to avoid a default of the application and the product. nxp semiconducto rs does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. non-automotive qualified products ? unless the data sheet of an nxp semiconductors product expressly states that the product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive sp ecifications and standards, customer (a) shall use the product without nx p semiconductors? warranty of the document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objec tive specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 89 of 91 continued >> nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
p89lpc9151_61_71_2 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 9 february 2010 90 of 91 continued >> nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 additional features . . . . . . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 7 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 9 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 functional description . . . . . . . . . . . . . . . . . . 16 7.1 special function registers . . . . . . . . . . . . . . . . 16 7.2 enhanced cpu . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3 clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3.1 clock definitions . . . . . . . . . . . . . . . . . . . . . . . 38 7.3.2 cpu clock (oscclk). . . . . . . . . . . . . . . . . . . 38 7.4 clock output (p89lpc9171) . . . . . . . . . . . . . . 38 7.5 on-chip rc oscillator option . . . . . . . . . . . . . . 38 7.6 watchdog oscillator option . . . . . . . . . . . . . . . 39 7.7 external clock input option . . . . . . . . . . . . . . . 39 7.8 clock sources switch on the fly. . . . . . . . . . . . 39 7.9 cclk wake-up delay . . . . . . . . . . . . . . . . . . . 40 7.10 cclk modification: divm register . . . . . . . . . 40 7.11 low power select . . . . . . . . . . . . . . . . . . . . . . 40 7.12 memory organization . . . . . . . . . . . . . . . . . . . 41 7.13 data ram arrangement . . . . . . . . . . . . . . . . . 41 7.14 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.14.1 external interrupt inputs . . . . . . . . . . . . . . . . . 42 7.15 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.15.1 port configurations . . . . . . . . . . . . . . . . . . . . . 44 7.15.1.1 quasi-bidirectional outp ut configuration . . . . . 44 7.15.1.2 open-drain output configuration . . . . . . . . . . . 45 7.15.1.3 input-only configuration . . . . . . . . . . . . . . . . . 45 7.15.1.4 push-pull output configuration . . . . . . . . . . . . 45 7.15.2 port 0 analog functions . . . . . . . . . . . . . . . . . . 45 7.15.3 additional port features. . . . . . . . . . . . . . . . . . 45 7.16 power monitoring functions . . . . . . . . . . . . . . 46 7.16.1 brownout detection . . . . . . . . . . . . . . . . . . . . . 46 7.16.2 power-on detection. . . . . . . . . . . . . . . . . . . . . 46 7.17 power reduction modes . . . . . . . . . . . . . . . . . 46 7.17.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.17.2 power-down mode . . . . . . . . . . . . . . . . . . . . . 47 7.17.3 total power-down mode . . . . . . . . . . . . . . . . . 47 7.18 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.18.1 reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.19 timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 48 7.19.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.19.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.19.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.19.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.19.5 mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.19.6 timer overflow toggle output . . . . . . . . . . . . . 49 7.20 rtc/system timer . . . . . . . . . . . . . . . . . . . . . 49 7.21 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.21.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.21.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.21.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.21.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.21.5 baud rate generator and selection. . . . . . . . . 50 7.21.6 framing error . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.21.7 break detect. . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.21.8 double buffering. . . . . . . . . . . . . . . . . . . . . . . 50 7.21.9 transmit interrupts with double buffering enabled (modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . . . 51 7.21.10 the 9 th bit (bit 8) in double buffering (modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.22 i 2 c-bus serial interface. . . . . . . . . . . . . . . . . . 51 7.23 spi (P89LPC9161) . . . . . . . . . . . . . . . . . . . . 53 7.23.1 typical spi configurations . . . . . . . . . . . . . . . 54 7.24 analog comparators. . . . . . . . . . . . . . . . . . . . 55 7.24.1 internal reference voltage . . . . . . . . . . . . . . . 56 7.24.2 comparator interrupt . . . . . . . . . . . . . . . . . . . 56 7.24.3 comparators and power reduction modes . . . 56 7.25 kbi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.26 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 57 7.27 additional features . . . . . . . . . . . . . . . . . . . . . 58 7.27.1 software reset . . . . . . . . . . . . . . . . . . . . . . . . 58 7.27.2 dual data pointers . . . . . . . . . . . . . . . . . . . . . 58 7.28 flash program memory . . . . . . . . . . . . . . . . . 58 7.28.1 general description . . . . . . . . . . . . . . . . . . . . 58 7.28.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.28.3 flash organization . . . . . . . . . . . . . . . . . . . . . 59 7.28.4 using flash as data storage . . . . . . . . . . . . . . 59 7.28.5 flash programming and erasing . . . . . . . . . . 59 7.28.6 icp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.28.7 iap-lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.29 user configuration bytes . . . . . . . . . . . . . . . . 60 7.30 user sector security bytes . . . . . . . . . . . . . . . 60 8 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.1 general description . . . . . . . . . . . . . . . . . . . . 60 8.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . 61 8.4 adc operating modes . . . . . . . . . . . . . . . . . . 61 8.4.1 fixed channel, single conversion mode. . . . . 61
nxp semiconductors p89lpc9151/9161/9171 8-bit microcontroller with 8-bit adc ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 9 february 2010 document identifier: p89lpc9151_61_71_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 8.4.2 fixed channel, contin uous conversion mode . 61 8.4.3 auto scan, single conversion mode . . . . . . . . 61 8.4.4 auto scan, continuous c onversion mode . . . . 61 8.4.5 dual channel, continuous conversion mode . . 62 8.4.6 single step mode . . . . . . . . . . . . . . . . . . . . . . 62 8.5 conversion start modes . . . . . . . . . . . . . . . . . 62 8.5.1 timer triggered start . . . . . . . . . . . . . . . . . . . . 62 8.5.2 start immediately . . . . . . . . . . . . . . . . . . . . . . 62 8.5.3 edge triggered . . . . . . . . . . . . . . . . . . . . . . . . 62 8.6 boundary limits interrupt . . . . . . . . . . . . . . . . . 62 8.7 dac output to a port pin with high output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.8 clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.9 power-down and idle mode . . . . . . . . . . . . . . 63 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 64 10 static characteristics. . . . . . . . . . . . . . . . . . . . 65 10.1 current characteristics . . . . . . . . . . . . . . . . . . 67 10.2 internal rc/watchdog oscillator characteristics 71 10.3 bod characteristics . . . . . . . . . . . . . . . . . . . . 74 11 dynamic characteristics . . . . . . . . . . . . . . . . . 75 11.1 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12 other characteristics . . . . . . . . . . . . . . . . . . . . 81 12.1 comparator electrical characteristics . . . . . . . 81 12.2 adc electrical characteristics . . . . . . . . . . . . . 82 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 84 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 86 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 87 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 88 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 88 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 89 17 contact information. . . . . . . . . . . . . . . . . . . . . 89 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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